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4c1f3c24db
into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM. There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier. The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today. I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something). I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily. llvm-svn: 171366
84 lines
2.6 KiB
C++
84 lines
2.6 KiB
C++
//===- AMDGPUMCInstLower.cpp - Lower AMDGPU MachineInstr to an MCInst -----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief Code to lower AMDGPU MachineInstrs to their corresponding MCInst.
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//
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//===----------------------------------------------------------------------===//
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//
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#include "AMDGPUMCInstLower.h"
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#include "AMDGPUAsmPrinter.h"
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#include "R600InstrInfo.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/Support/ErrorHandling.h"
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using namespace llvm;
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AMDGPUMCInstLower::AMDGPUMCInstLower(MCContext &ctx):
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Ctx(ctx)
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{ }
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void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
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OutMI.setOpcode(MI->getOpcode());
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for (unsigned i = 0, e = MI->getNumExplicitOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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MCOperand MCOp;
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switch (MO.getType()) {
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default:
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llvm_unreachable("unknown operand type");
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case MachineOperand::MO_FPImmediate: {
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const APFloat &FloatValue = MO.getFPImm()->getValueAPF();
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assert(&FloatValue.getSemantics() == &APFloat::IEEEsingle &&
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"Only floating point immediates are supported at the moment.");
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MCOp = MCOperand::CreateFPImm(FloatValue.convertToFloat());
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break;
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}
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case MachineOperand::MO_Immediate:
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MCOp = MCOperand::CreateImm(MO.getImm());
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break;
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case MachineOperand::MO_Register:
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MCOp = MCOperand::CreateReg(MO.getReg());
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break;
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case MachineOperand::MO_MachineBasicBlock:
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MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create(
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MO.getMBB()->getSymbol(), Ctx));
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}
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OutMI.addOperand(MCOp);
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}
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}
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void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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AMDGPUMCInstLower MCInstLowering(OutContext);
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if (MI->isBundle()) {
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const MachineBasicBlock *MBB = MI->getParent();
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MachineBasicBlock::const_instr_iterator I = MI;
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++I;
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while (I != MBB->end() && I->isInsideBundle()) {
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MCInst MCBundleInst;
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const MachineInstr *BundledInst = I;
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MCInstLowering.lower(BundledInst, MCBundleInst);
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OutStreamer.EmitInstruction(MCBundleInst);
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++I;
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}
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} else {
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MCInst TmpInst;
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MCInstLowering.lower(MI, TmpInst);
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OutStreamer.EmitInstruction(TmpInst);
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}
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}
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