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649e8ff0ee
Using REG_SEQUENCE for BUILD_VECTOR rather than a series of INSERT_SUBREG
instructions should make it easier for the register allocator to coalasce
unnecessary copies.
v2:
- Use an SGPR register class if all the operands of BUILD_VECTOR are
SGPRs.
llvm-svn: 188427
68 lines
2.3 KiB
C++
68 lines
2.3 KiB
C++
//===-- AMDGPURegisterInfo.cpp - AMDGPU Register Information -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief Parent TargetRegisterInfo class common to all hw codegen targets.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPURegisterInfo.h"
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#include "AMDGPUTargetMachine.h"
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using namespace llvm;
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AMDGPURegisterInfo::AMDGPURegisterInfo(TargetMachine &tm)
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: AMDGPUGenRegisterInfo(0),
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TM(tm)
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{ }
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//===----------------------------------------------------------------------===//
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// Function handling callbacks - Functions are a seldom used feature of GPUS, so
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// they are not supported at this time.
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//===----------------------------------------------------------------------===//
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const uint16_t AMDGPURegisterInfo::CalleeSavedReg = AMDGPU::NoRegister;
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const uint16_t* AMDGPURegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
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const {
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return &CalleeSavedReg;
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}
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void AMDGPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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int SPAdj,
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unsigned FIOperandNum,
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RegScavenger *RS) const {
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assert(!"Subroutines not supported yet");
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}
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unsigned AMDGPURegisterInfo::getFrameRegister(const MachineFunction &MF) const {
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assert(!"Subroutines not supported yet");
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return 0;
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}
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unsigned AMDGPURegisterInfo::getSubRegFromChannel(unsigned Channel) const {
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static const unsigned SubRegs[] = {
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AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, AMDGPU::sub4,
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AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, AMDGPU::sub8, AMDGPU::sub9,
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AMDGPU::sub10, AMDGPU::sub11, AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14,
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AMDGPU::sub15
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};
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assert (Channel < array_lengthof(SubRegs));
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return SubRegs[Channel];
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}
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unsigned AMDGPURegisterInfo::getIndirectSubReg(unsigned IndirectIndex) const {
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return getSubRegFromChannel(IndirectIndex);
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}
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#define GET_REGINFO_TARGET_DESC
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#include "AMDGPUGenRegisterInfo.inc"
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