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https://github.com/RPCS3/llvm-mirror.git
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3cad3632a2
Improved handling of fma, floating point min/max, additional load/store instructions for floating point types. Patch by Jyotsna Verma. llvm-svn: 279239
251 lines
7.6 KiB
C++
251 lines
7.6 KiB
C++
//===-- HexagonRegisterInfo.cpp - Hexagon Register Information ------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Hexagon implementation of the TargetRegisterInfo
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// class.
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//
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//===----------------------------------------------------------------------===//
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#include "HexagonRegisterInfo.h"
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#include "Hexagon.h"
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#include "HexagonMachineFunctionInfo.h"
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#include "HexagonSubtarget.h"
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#include "HexagonTargetMachine.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/Type.h"
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#include "llvm/MC/MachineLocation.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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HexagonRegisterInfo::HexagonRegisterInfo()
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: HexagonGenRegisterInfo(Hexagon::R31) {}
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bool HexagonRegisterInfo::isEHReturnCalleeSaveReg(unsigned R) const {
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return R == Hexagon::R0 || R == Hexagon::R1 || R == Hexagon::R2 ||
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R == Hexagon::R3 || R == Hexagon::D0 || R == Hexagon::D1;
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}
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bool HexagonRegisterInfo::isCalleeSaveReg(unsigned Reg) const {
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return Hexagon::R16 <= Reg && Reg <= Hexagon::R27;
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}
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const MCPhysReg *
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HexagonRegisterInfo::getCallerSavedRegs(const MachineFunction *MF,
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const TargetRegisterClass *RC) const {
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using namespace Hexagon;
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static const MCPhysReg Int32[] = {
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R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, 0
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};
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static const MCPhysReg Int64[] = {
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D0, D1, D2, D3, D4, D5, D6, D7, 0
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};
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static const MCPhysReg Pred[] = {
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P0, P1, P2, P3, 0
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};
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static const MCPhysReg VecSgl[] = {
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V0, V1, V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13,
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V14, V15, V16, V17, V18, V19, V20, V21, V22, V23, V24, V25, V26, V27,
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V28, V29, V30, V31, 0
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};
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static const MCPhysReg VecDbl[] = {
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W0, W1, W2, W3, W4, W5, W6, W7, W8, W9, W10, W11, W12, W13, W14, W15, 0
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};
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switch (RC->getID()) {
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case IntRegsRegClassID:
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return Int32;
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case DoubleRegsRegClassID:
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return Int64;
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case PredRegsRegClassID:
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return Pred;
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case VectorRegsRegClassID:
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case VectorRegs128BRegClassID:
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return VecSgl;
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case VecDblRegsRegClassID:
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case VecDblRegs128BRegClassID:
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return VecDbl;
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default:
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break;
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}
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static const MCPhysReg Empty[] = { 0 };
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#ifndef NDEBUG
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dbgs() << "Register class: " << getRegClassName(RC) << "\n";
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#endif
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llvm_unreachable("Unexpected register class");
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return Empty;
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}
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const MCPhysReg *
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HexagonRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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static const MCPhysReg CalleeSavedRegsV3[] = {
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Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
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Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23,
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Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0
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};
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// Functions that contain a call to __builtin_eh_return also save the first 4
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// parameter registers.
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static const MCPhysReg CalleeSavedRegsV3EHReturn[] = {
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Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3,
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Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
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Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23,
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Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0
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};
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bool HasEHReturn = MF->getInfo<HexagonMachineFunctionInfo>()->hasEHReturn();
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switch (MF->getSubtarget<HexagonSubtarget>().getHexagonArchVersion()) {
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case HexagonSubtarget::V4:
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case HexagonSubtarget::V5:
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case HexagonSubtarget::V55:
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case HexagonSubtarget::V60:
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return HasEHReturn ? CalleeSavedRegsV3EHReturn : CalleeSavedRegsV3;
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}
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llvm_unreachable("Callee saved registers requested for unknown architecture "
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"version");
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}
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BitVector HexagonRegisterInfo::getReservedRegs(const MachineFunction &MF)
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const {
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BitVector Reserved(getNumRegs());
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Reserved.set(Hexagon::R29);
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Reserved.set(Hexagon::R30);
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Reserved.set(Hexagon::R31);
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Reserved.set(Hexagon::PC);
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Reserved.set(Hexagon::D14);
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Reserved.set(Hexagon::D15);
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Reserved.set(Hexagon::LC0);
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Reserved.set(Hexagon::LC1);
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Reserved.set(Hexagon::SA0);
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Reserved.set(Hexagon::SA1);
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Reserved.set(Hexagon::UGP);
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Reserved.set(Hexagon::GP);
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Reserved.set(Hexagon::CS0);
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Reserved.set(Hexagon::CS1);
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Reserved.set(Hexagon::CS);
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Reserved.set(Hexagon::USR);
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return Reserved;
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}
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void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, unsigned FIOp,
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RegScavenger *RS) const {
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//
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// Hexagon_TODO: Do we need to enforce this for Hexagon?
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assert(SPAdj == 0 && "Unexpected");
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MachineInstr &MI = *II;
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MachineBasicBlock &MB = *MI.getParent();
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MachineFunction &MF = *MB.getParent();
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auto &HST = MF.getSubtarget<HexagonSubtarget>();
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auto &HII = *HST.getInstrInfo();
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auto &HFI = *HST.getFrameLowering();
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unsigned BP = 0;
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int FI = MI.getOperand(FIOp).getIndex();
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// Select the base pointer (BP) and calculate the actual offset from BP
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// to the beginning of the object at index FI.
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int Offset = HFI.getFrameIndexReference(MF, FI, BP);
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// Add the offset from the instruction.
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int RealOffset = Offset + MI.getOperand(FIOp+1).getImm();
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bool IsKill = false;
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unsigned Opc = MI.getOpcode();
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switch (Opc) {
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case Hexagon::PS_fia:
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MI.setDesc(HII.get(Hexagon::A2_addi));
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MI.getOperand(FIOp).ChangeToImmediate(RealOffset);
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MI.RemoveOperand(FIOp+1);
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return;
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case Hexagon::PS_fi:
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// Set up the instruction for updating below.
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MI.setDesc(HII.get(Hexagon::A2_addi));
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break;
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}
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if (!HII.isValidOffset(Opc, RealOffset)) {
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// If the offset is not valid, calculate the address in a temporary
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// register and use it with offset 0.
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auto &MRI = MF.getRegInfo();
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unsigned TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
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const DebugLoc &DL = MI.getDebugLoc();
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BuildMI(MB, II, DL, HII.get(Hexagon::A2_addi), TmpR)
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.addReg(BP)
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.addImm(RealOffset);
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BP = TmpR;
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RealOffset = 0;
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IsKill = true;
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}
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MI.getOperand(FIOp).ChangeToRegister(BP, false, false, IsKill);
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MI.getOperand(FIOp+1).ChangeToImmediate(RealOffset);
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}
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unsigned HexagonRegisterInfo::getRARegister() const {
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return Hexagon::R31;
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}
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unsigned HexagonRegisterInfo::getFrameRegister(const MachineFunction
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&MF) const {
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const HexagonFrameLowering *TFI = getFrameLowering(MF);
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if (TFI->hasFP(MF))
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return getFrameRegister();
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return getStackRegister();
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}
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unsigned HexagonRegisterInfo::getFrameRegister() const {
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return Hexagon::R30;
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}
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unsigned HexagonRegisterInfo::getStackRegister() const {
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return Hexagon::R29;
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}
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bool HexagonRegisterInfo::useFPForScavengingIndex(const MachineFunction &MF)
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const {
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return MF.getSubtarget<HexagonSubtarget>().getFrameLowering()->hasFP(MF);
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}
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unsigned HexagonRegisterInfo::getFirstCallerSavedNonParamReg() const {
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return Hexagon::R6;
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}
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#define GET_REGINFO_TARGET_DESC
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#include "HexagonGenRegisterInfo.inc"
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