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llvm-mirror/test/DebugInfo/MIR
Vedant Kumar 5033576468 [entry values] ARM: Add a describeLoadedValue override (PR45025)
As a narrow stopgap for the assertion failure described in PR45025, add
a describeLoadedValue override to ARMBaseInstrInfo and use it to detect
copies in which the forwarding reg is a super/sub reg of the copy
destination. For the moment this is unsupported.

Several follow ups are possible:

1) Handle VORRq. At the moment, we do not, because isCopyInstrImpl
   returns early when !MI.isMoveReg().

2) In the case where forwarding reg is a super-reg of the copy
   destination, we should be able to describe the forwarding reg as a
   subreg within the copy destination. I'm not 100% sure about this, but
   it looks like that's what's done in AArch64InstrInfo.

3) In the case where the forwarding reg is a sub-reg of the copy
   destination, maybe we could describe the forwarding reg using the
   copy destinaion and a DW_OP_LLVM_fragment (I guess this should be
   possible after D75036).

https://bugs.llvm.org/show_bug.cgi?id=45025
rdar://59772698

Differential Revision: https://reviews.llvm.org/D75273
2020-02-28 14:30:40 -08:00
..
AArch64 [DebugInfo] Describe call site values for chains of expression producing instrs 2020-02-27 11:18:51 +01:00
ARM [entry values] ARM: Add a describeLoadedValue override (PR45025) 2020-02-28 14:30:40 -08:00
Hexagon Revert "Reland "[DebugInfo] Enable the debug entry values feature by default"" 2020-02-20 14:41:39 +01:00
Mips
SystemZ Revert "Reland "[DebugInfo] Enable the debug entry values feature by default"" 2020-02-20 14:41:39 +01:00
X86 [NFC] [Test commit] Testing commit access with new email 2020-02-28 12:01:52 +01:00
lit.local.cfg