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107b591be0
In the WebAssembly target, we would like to allow alloca in two address spaces. The alloca instruction already has an address space argument, but the verifier asserts that the address space of an alloca is the default alloca address space from the datalayout. This patch removes this restriction. Targets that would like to impose additional restrictions should do so via target-specific verification passes. Differential Revision: https://reviews.llvm.org/D101045
25 lines
844 B
LLVM
25 lines
844 B
LLVM
; RUN: llvm-as < %s -o %t.bc -data-layout=A5 2>&1 | FileCheck -check-prefixes=AS %s
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; RUN: llvm-dis < %t.bc | FileCheck -check-prefixes=DIS %s
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; RUN: opt < %s -S -data-layout=A5 2>&1 | FileCheck -check-prefixes=AS %s
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; RUN: opt < %t.bc -S | FileCheck -check-prefixes=DIS %s
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define void @foo() {
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entry:
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; DIS: target datalayout = "A5"
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; DIS: %tmp = alloca i32, align 4, addrspace(5)
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%tmp = alloca i32, addrspace(5)
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call void @llvm.dbg.value(
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metadata i8* undef,
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metadata !DILocalVariable(scope: !1),
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metadata !DIExpression())
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; AS: llvm.dbg.value intrinsic requires a !dbg attachment
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; AS: warning: ignoring invalid debug info in <stdin>
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ret void
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}
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declare void @llvm.dbg.value(metadata, metadata, metadata)
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!llvm.module.flags = !{!0}
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!0 = !{i32 2, !"Debug Info Version", i32 3}
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!1 = distinct !DISubprogram(name: "foo")
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