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89f6a784c5
- Keep implicit defs from inline-asm instructions. - Treat register references from inline-asm as fixed. llvm-svn: 267936
37 lines
1.4 KiB
LLVM
37 lines
1.4 KiB
LLVM
; RUN: llc -march=hexagon < %s
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; REQUIRES: asserts
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target datalayout = "e-m:e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a:0-n16:32"
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target triple = "hexagon"
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@x = common global i32* null, align 4
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; Function Attrs: nounwind
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define i32 @inotify_init() #0 {
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entry:
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%0 = tail call i32 asm sideeffect "trap0(#1);\0A", "={r0},{r6},~{memory}"(i32 1043) #1, !srcloc !1
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%cmp = icmp sgt i32 %0, -4096
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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%sub = sub nsw i32 0, %0
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%1 = load i32*, i32** @x, align 4, !tbaa !2
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store i32 %sub, i32* %1, align 4, !tbaa !6
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br label %if.end
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if.end: ; preds = %if.then, %entry
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%retval1.0 = phi i32 [ -1, %if.then ], [ %0, %entry ]
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ret i32 %retval1.0
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}
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attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" }
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attributes #1 = { nounwind }
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!1 = !{i32 155}
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!2 = !{!3, !3, i64 0}
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!3 = !{!"any pointer", !4, i64 0}
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!4 = !{!"omnipotent char", !5, i64 0}
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!5 = !{!"Simple C/C++ TBAA"}
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!6 = !{!7, !7, i64 0}
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!7 = !{!"long", !4, i64 0}
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