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e37295579e
Software pipelining is an optimization for improving ILP by overlapping loop iterations. Swing Modulo Scheduling (SMS) is an implementation of software pipelining that attempts to reduce register pressure and generate efficient pipelines with a low compile-time cost. This implementaion of SMS is a target-independent back-end pass. When enabled, the pass should run just prior to the register allocation pass, while the machine IR is in SSA form. If the pass is successful, then the original loop is replaced by the optimized loop. The optimized loop contains one or more prolog blocks, the pipelined kernel, and one or more epilog blocks. This pass is enabled for Hexagon only. To enable for other targets, a couple of target specific hooks must be implemented, and the pass needs to be called from the target's TargetMachine implementation. Differential Review: http://reviews.llvm.org/D16829 llvm-svn: 277169
66 lines
3.1 KiB
LLVM
66 lines
3.1 KiB
LLVM
; RUN: llc -fp-contract=fast -O3 -march=hexagon -mcpu=hexagonv5 < %s
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; REQUIRES: asserts
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; Test that the pipeliner doesn't ICE due because the PHI generation
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; code in the epilog does not attempt to reuse an existing PHI.
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define void @test(float* noalias %srcImg, i32 %width, float* noalias %dstImg) {
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entry.split:
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%shr = lshr i32 %width, 1
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%incdec.ptr253 = getelementptr inbounds float, float* %dstImg, i32 2
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br i1 undef, label %for.body, label %for.end
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for.body:
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%dst.21518.reg2mem.0 = phi float* [ null, %while.end712 ], [ %incdec.ptr253, %entry.split ]
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%dstEnd.01519 = phi float* [ %add.ptr725, %while.end712 ], [ undef, %entry.split ]
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%add.ptr367 = getelementptr inbounds float, float* %srcImg, i32 undef
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%dst.31487 = getelementptr inbounds float, float* %dst.21518.reg2mem.0, i32 1
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br i1 undef, label %while.body661.preheader, label %while.end712
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while.body661.preheader:
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%scevgep1941 = getelementptr float, float* %add.ptr367, i32 1
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br label %while.body661.ur
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while.body661.ur:
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%lsr.iv1942 = phi float* [ %scevgep1941, %while.body661.preheader ], [ undef, %while.body661.ur ]
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%col1.31508.reg2mem.0.ur = phi float [ %col3.31506.reg2mem.0.ur, %while.body661.ur ], [ undef, %while.body661.preheader ]
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%col4.31507.reg2mem.0.ur = phi float [ %add710.ur, %while.body661.ur ], [ 0.000000e+00, %while.body661.preheader ]
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%col3.31506.reg2mem.0.ur = phi float [ %add689.ur, %while.body661.ur ], [ undef, %while.body661.preheader ]
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%dst.41511.ur = phi float* [ %incdec.ptr674.ur, %while.body661.ur ], [ %dst.31487, %while.body661.preheader ]
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%mul662.ur = fmul float %col1.31508.reg2mem.0.ur, 4.000000e+00
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%add663.ur = fadd float undef, %mul662.ur
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%add665.ur = fadd float %add663.ur, undef
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%add667.ur = fadd float undef, %add665.ur
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%add669.ur = fadd float undef, %add667.ur
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%add670.ur = fadd float %col4.31507.reg2mem.0.ur, %add669.ur
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%conv673.ur = fmul float %add670.ur, 3.906250e-03
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%incdec.ptr674.ur = getelementptr inbounds float, float* %dst.41511.ur, i32 1
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store float %conv673.ur, float* %dst.41511.ur, align 4
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%scevgep1959 = getelementptr float, float* %lsr.iv1942, i32 -1
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%0 = load float, float* %scevgep1959, align 4
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%mul680.ur = fmul float %0, 4.000000e+00
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%add681.ur = fadd float undef, %mul680.ur
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%add684.ur = fadd float undef, %add681.ur
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%add687.ur = fadd float undef, %add684.ur
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%add689.ur = fadd float undef, %add687.ur
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%add699.ur = fadd float undef, undef
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%add703.ur = fadd float undef, %add699.ur
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%add707.ur = fadd float undef, %add703.ur
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%add710.ur = fadd float undef, %add707.ur
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%cmp660.ur = icmp ult float* %incdec.ptr674.ur, %dstEnd.01519
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br i1 %cmp660.ur, label %while.body661.ur, label %while.end712
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while.end712:
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%dst.4.lcssa.reg2mem.0 = phi float* [ %dst.31487, %for.body ], [ undef, %while.body661.ur ]
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%conv721 = fpext float undef to double
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%mul722 = fmul double %conv721, 0x3F7111112119E8FB
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%conv723 = fptrunc double %mul722 to float
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store float %conv723, float* %dst.4.lcssa.reg2mem.0, align 4
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%add.ptr725 = getelementptr inbounds float, float* %dstEnd.01519, i32 %shr
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%cmp259 = icmp ult i32 undef, undef
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br i1 %cmp259, label %for.body, label %for.end
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for.end:
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ret void
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}
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