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Mirror of https://github.com/RPCS3/llvm-mirror
512a21080d
Summary: A few instructions (mostly cvt.d.w and similar) are causing problems with -mfp64 and -mno-odd-spreg and it looks like fixing it properly may take several weeks. In the meantime, let's disable the odd-numbered double-precision registers so that the generated code is at least valid. The problem is that instructions like cvt.d.w read from the 32-bit low subregister of a double-precision FPU register. This often leads to the compiler to inserting moves to transfer a GPR32 to a FGR32 using mtc1. Such moves violate the rules against 32-bit writes to odd-numbered FPU registers imposed by -mno-odd-spreg. By disabling the odd-numbered double-precision registers, it becomes impossible for the 32-bit low subregister to be odd-numbered. This fixes numerous test-suite failures when compiling for the FP64A ABI ('-mfp64 -mno-odd-spreg'). There is no LLVM test case because it's difficult to test that odd-numbered FPU registers are not allocatable. Instead, we depend on the assembler (GAS and -fintegrated-as) raising errors when the rules are violated. Differential Revision: http://reviews.llvm.org/D4532 llvm-svn: 213160 |
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cmake | ||
docs | ||
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include | ||
lib | ||
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.arcconfig | ||
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.gitignore | ||
CMakeLists.txt | ||
CODE_OWNERS.TXT | ||
configure | ||
CREDITS.TXT | ||
LICENSE.TXT | ||
llvm.spec.in | ||
LLVMBuild.txt | ||
Makefile | ||
Makefile.common | ||
Makefile.config.in | ||
Makefile.rules | ||
README.txt |
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