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3cdf780204
This is a recommit of r256004 which was reverted in r256160. The issue was the incorrect promotion for half and byte loads transformed into mov instructions. This fix will replace half and byte type loads only with bit field extracts. Original commit message: This change promotes load instructions which directly read from stored by replacing them with mov instructions. If the store is wider than the load, the load will be replaced with a bitfield extract. For example : STRWui %W1, %X0, 1 %W0 = LDRHHui %X0, 3 becomes STRWui %W1, %X0, 1 %W0 = UBFMWri %W1, 16, 31 llvm-svn: 256249
30 lines
894 B
LLVM
30 lines
894 B
LLVM
; RUN: llc -march=arm64 -mcpu=cyclone < %s | FileCheck %s
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; CHECK: foo
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; CHECK: str w[[REG0:[0-9]+]], [x19, #264]
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; CHECK: mov w[[REG1:[0-9]+]], w[[REG0]]
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; CHECK: str w[[REG1]], [x19, #132]
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define i32 @foo(i32 %a) nounwind {
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%retval = alloca i32, align 4
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%a.addr = alloca i32, align 4
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%arr = alloca [32 x i32], align 4
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%i = alloca i32, align 4
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%arr2 = alloca [32 x i32], align 4
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%j = alloca i32, align 4
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store i32 %a, i32* %a.addr, align 4
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%tmp = load i32, i32* %a.addr, align 4
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%tmp1 = zext i32 %tmp to i64
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%v = mul i64 4, %tmp1
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%vla = alloca i8, i64 %v, align 4
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%tmp2 = bitcast i8* %vla to i32*
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%tmp3 = load i32, i32* %a.addr, align 4
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store i32 %tmp3, i32* %i, align 4
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%tmp4 = load i32, i32* %a.addr, align 4
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store i32 %tmp4, i32* %j, align 4
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%tmp5 = load i32, i32* %j, align 4
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store i32 %tmp5, i32* %retval
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%x = load i32, i32* %retval
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ret i32 %x
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}
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