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0fa09433f0
Most immediates are printed in Aarch64InstPrinter using 'formatImm' macro, but not all of them. Implementation contains following rules: - floating point immediates are always printed as decimal - signed integer immediates are printed depends on flag settings (for negative values 'formatImm' macro prints the value as i.e -0x01 which may be convenient when imm is an address or offset) - logical immediates are always printed as hex - the 64-bit immediate for advSIMD, encoded in "a🅱️c:d:e:f:g:h" is always printed as hex - the 64-bit immedaite in exception generation instructions like: brk, dcps1, dcps2, dcps3, hlt, hvc, smc, svc is always printed as hex - the rest of immediates is printed depends on availability of -print-imm-hex Signed-off-by: Maciej Gabka <maciej.gabka@arm.com> Signed-off-by: Paul Osmialowski <pawel.osmialowski@arm.com> Differential Revision: http://reviews.llvm.org/D16929 llvm-svn: 269446
38 lines
1.2 KiB
LLVM
38 lines
1.2 KiB
LLVM
; RUN: llc -O0 -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
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; Test load/store of global value from global offset table.
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@seed = common global i64 0, align 8
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define void @Initrand() nounwind {
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entry:
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; CHECK: @Initrand
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; CHECK: adrp [[REG:x[0-9]+]], _seed@GOTPAGE
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; CHECK: ldr [[REG2:x[0-9]+]], {{\[}}[[REG]], _seed@GOTPAGEOFF{{\]}}
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; CHECK: str {{x[0-9]+}}, {{\[}}[[REG2]]{{\]}}
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store i64 74755, i64* @seed, align 8
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ret void
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}
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define i32 @Rand() nounwind {
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entry:
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; CHECK: @Rand
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; CHECK: adrp [[REG1:x[0-9]+]], _seed@GOTPAGE
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; CHECK: ldr [[REG2:x[0-9]+]], {{\[}}[[REG1]], _seed@GOTPAGEOFF{{\]}}
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; CHECK: movz [[REG3:x[0-9]+]], #13849
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; CHECK: movz [[REG4:x[0-9]+]], #1309
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; CHECK: ldr [[REG5:x[0-9]+]], {{\[}}[[REG2]]{{\]}}
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; CHECK: mul [[REG6:x[0-9]+]], [[REG5]], [[REG4]]
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; CHECK: add [[REG7:x[0-9]+]], [[REG6]], [[REG3]]
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; CHECK: and [[REG8:x[0-9]+]], [[REG7]], #0xffff
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; CHECK: str [[REG8]], {{\[}}[[REG1]]{{\]}}
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; CHECK: ldr {{x[0-9]+}}, {{\[}}[[REG1]]{{\]}}
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%0 = load i64, i64* @seed, align 8
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%mul = mul nsw i64 %0, 1309
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%add = add nsw i64 %mul, 13849
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%and = and i64 %add, 65535
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store i64 %and, i64* @seed, align 8
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%1 = load i64, i64* @seed, align 8
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%conv = trunc i64 %1 to i32
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ret i32 %conv
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}
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