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30a743add7
Summary: They correspond to BUFFER_LOAD/STORE_DWORD[_X2,X3,X4] and mostly behave like llvm.amdgcn.buffer.load/store.format. They will be used by Mesa for SSBO and atomic counters at least when robust buffer access behavior is desired. (These instructions perform no format conversion and do buffer range checking per component.) As a side effect of sharing patterns with llvm.amdgcn.buffer.store.format, it has become trivial to add support for the f32 and v2f32 variants of that intrinsic, so the patch does so. Also DAG-ify (and fix) some tests that I noticed intermittent failures in while developing this patch. Some tests were (temporarily) adjusted for the required mayLoad/hasSideEffects changes to the BUFFER_STORE_DWORD* instructions. See also http://reviews.llvm.org/D18291. Reviewers: arsenm, tstellarAMD, mareko Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D18292 llvm-svn: 266126
44 lines
1.6 KiB
LLVM
44 lines
1.6 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; Make sure the add and load are reduced to 32-bits even with the
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; bitcast to vector.
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; GCN-LABEL: {{^}}bitcast_int_to_vector_extract_0:
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; GCN-DAG: s_load_dword [[B:s[0-9]+]]
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; GCN-DAG: buffer_load_dword [[A:v[0-9]+]]
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; GCN: v_add_i32_e32 [[ADD:v[0-9]+]], vcc, [[B]], [[A]]
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; GCN: buffer_store_dword [[ADD]]
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define void @bitcast_int_to_vector_extract_0(i32 addrspace(1)* %out, i64 addrspace(1)* %in, i64 %b) {
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%a = load i64, i64 addrspace(1)* %in
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%add = add i64 %a, %b
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%val.bc = bitcast i64 %add to <2 x i32>
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%extract = extractelement <2 x i32> %val.bc, i32 0
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store i32 %extract, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}bitcast_fp_to_vector_extract_0:
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; GCN: buffer_load_dwordx2
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; GCN: v_add_f64
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; GCN: buffer_store_dword v
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define void @bitcast_fp_to_vector_extract_0(i32 addrspace(1)* %out, double addrspace(1)* %in, double %b) {
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%a = load double, double addrspace(1)* %in
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%add = fadd double %a, %b
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%val.bc = bitcast double %add to <2 x i32>
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%extract = extractelement <2 x i32> %val.bc, i32 0
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store i32 %extract, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}bitcast_int_to_fpvector_extract_0:
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; GCN: buffer_load_dwordx2
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; GCN: v_add_i32
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; GCN: buffer_store_dword
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define void @bitcast_int_to_fpvector_extract_0(float addrspace(1)* %out, i64 addrspace(1)* %in, i64 %b) {
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%a = load i64, i64 addrspace(1)* %in
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%add = add i64 %a, %b
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%val.bc = bitcast i64 %add to <2 x float>
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%extract = extractelement <2 x float> %val.bc, i32 0
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store float %extract, float addrspace(1)* %out
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ret void
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}
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