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https://github.com/RPCS3/llvm-mirror.git
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0c47b59618
We take the intersection of overflow flags while CSE'ing. This permits us to consider two instructions with different overflow behavior to be replaceable. llvm-svn: 267153
279 lines
6.5 KiB
LLVM
279 lines
6.5 KiB
LLVM
; RUN: opt < %s -S -early-cse | FileCheck %s
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; RUN: opt < %s -S -passes=early-cse | FileCheck %s
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declare void @llvm.assume(i1) nounwind
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; CHECK-LABEL: @test1(
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define void @test1(i8 %V, i32 *%P) {
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%A = bitcast i64 42 to double ;; dead
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%B = add i32 4, 19 ;; constant folds
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store i32 %B, i32* %P
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; CHECK-NEXT: store i32 23, i32* %P
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%C = zext i8 %V to i32
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%D = zext i8 %V to i32 ;; CSE
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store volatile i32 %C, i32* %P
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store volatile i32 %D, i32* %P
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; CHECK-NEXT: %C = zext i8 %V to i32
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; CHECK-NEXT: store volatile i32 %C
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; CHECK-NEXT: store volatile i32 %C
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%E = add i32 %C, %C
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%F = add i32 %C, %C
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store volatile i32 %E, i32* %P
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store volatile i32 %F, i32* %P
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; CHECK-NEXT: %E = add i32 %C, %C
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; CHECK-NEXT: store volatile i32 %E
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; CHECK-NEXT: store volatile i32 %E
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%G = add nuw i32 %C, %C
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store volatile i32 %G, i32* %P
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; CHECK-NEXT: store volatile i32 %E
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ret void
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}
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;; Simple load value numbering.
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; CHECK-LABEL: @test2(
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define i32 @test2(i32 *%P) {
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%V1 = load i32, i32* %P
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%V2 = load i32, i32* %P
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%Diff = sub i32 %V1, %V2
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ret i32 %Diff
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; CHECK: ret i32 0
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}
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; CHECK-LABEL: @test2a(
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define i32 @test2a(i32 *%P, i1 %b) {
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%V1 = load i32, i32* %P
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tail call void @llvm.assume(i1 %b)
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%V2 = load i32, i32* %P
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%Diff = sub i32 %V1, %V2
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ret i32 %Diff
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; CHECK: ret i32 0
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}
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;; Cross block load value numbering.
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; CHECK-LABEL: @test3(
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define i32 @test3(i32 *%P, i1 %Cond) {
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%V1 = load i32, i32* %P
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br i1 %Cond, label %T, label %F
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T:
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store i32 4, i32* %P
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ret i32 42
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F:
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%V2 = load i32, i32* %P
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%Diff = sub i32 %V1, %V2
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ret i32 %Diff
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; CHECK: F:
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; CHECK: ret i32 0
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}
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; CHECK-LABEL: @test3a(
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define i32 @test3a(i32 *%P, i1 %Cond, i1 %b) {
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%V1 = load i32, i32* %P
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br i1 %Cond, label %T, label %F
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T:
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store i32 4, i32* %P
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ret i32 42
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F:
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tail call void @llvm.assume(i1 %b)
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%V2 = load i32, i32* %P
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%Diff = sub i32 %V1, %V2
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ret i32 %Diff
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; CHECK: F:
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; CHECK: ret i32 0
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}
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;; Cross block load value numbering stops when stores happen.
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; CHECK-LABEL: @test4(
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define i32 @test4(i32 *%P, i1 %Cond) {
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%V1 = load i32, i32* %P
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br i1 %Cond, label %T, label %F
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T:
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ret i32 42
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F:
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; Clobbers V1
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store i32 42, i32* %P
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%V2 = load i32, i32* %P
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%Diff = sub i32 %V1, %V2
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ret i32 %Diff
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; CHECK: F:
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; CHECK: ret i32 %Diff
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}
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declare i32 @func(i32 *%P) readonly
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;; Simple call CSE'ing.
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; CHECK-LABEL: @test5(
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define i32 @test5(i32 *%P) {
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%V1 = call i32 @func(i32* %P)
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%V2 = call i32 @func(i32* %P)
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%Diff = sub i32 %V1, %V2
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ret i32 %Diff
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; CHECK: ret i32 0
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}
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;; Trivial Store->load forwarding
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; CHECK-LABEL: @test6(
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define i32 @test6(i32 *%P) {
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store i32 42, i32* %P
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%V1 = load i32, i32* %P
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ret i32 %V1
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; CHECK: ret i32 42
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}
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; CHECK-LABEL: @test6a(
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define i32 @test6a(i32 *%P, i1 %b) {
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store i32 42, i32* %P
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tail call void @llvm.assume(i1 %b)
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%V1 = load i32, i32* %P
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ret i32 %V1
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; CHECK: ret i32 42
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}
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;; Trivial dead store elimination.
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; CHECK-LABEL: @test7(
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define void @test7(i32 *%P) {
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store i32 42, i32* %P
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store i32 45, i32* %P
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ret void
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; CHECK-NEXT: store i32 45
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; CHECK-NEXT: ret void
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}
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;; Readnone functions aren't invalidated by stores.
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; CHECK-LABEL: @test8(
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define i32 @test8(i32 *%P) {
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%V1 = call i32 @func(i32* %P) readnone
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store i32 4, i32* %P
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%V2 = call i32 @func(i32* %P) readnone
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%Diff = sub i32 %V1, %V2
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ret i32 %Diff
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; CHECK: ret i32 0
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}
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;; Trivial DSE can't be performed across a readonly call. The call
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;; can observe the earlier write.
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; CHECK-LABEL: @test9(
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define i32 @test9(i32 *%P) {
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store i32 4, i32* %P
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%V1 = call i32 @func(i32* %P) readonly
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store i32 5, i32* %P
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ret i32 %V1
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; CHECK: store i32 4, i32* %P
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; CHECK-NEXT: %V1 = call i32 @func(i32* %P)
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; CHECK-NEXT: store i32 5, i32* %P
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; CHECK-NEXT: ret i32 %V1
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}
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;; Trivial DSE can be performed across a readnone call.
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; CHECK-LABEL: @test10
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define i32 @test10(i32 *%P) {
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store i32 4, i32* %P
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%V1 = call i32 @func(i32* %P) readnone
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store i32 5, i32* %P
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ret i32 %V1
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; CHECK-NEXT: %V1 = call i32 @func(i32* %P)
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; CHECK-NEXT: store i32 5, i32* %P
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; CHECK-NEXT: ret i32 %V1
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}
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;; Trivial dead store elimination - should work for an entire series of dead stores too.
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; CHECK-LABEL: @test11(
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define void @test11(i32 *%P) {
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store i32 42, i32* %P
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store i32 43, i32* %P
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store i32 44, i32* %P
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store i32 45, i32* %P
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ret void
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; CHECK-NEXT: store i32 45
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; CHECK-NEXT: ret void
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}
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; CHECK-LABEL: @test12(
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define i32 @test12(i1 %B, i32* %P1, i32* %P2) {
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%load0 = load i32, i32* %P1
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%1 = load atomic i32, i32* %P2 seq_cst, align 4
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%load1 = load i32, i32* %P1
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%sel = select i1 %B, i32 %load0, i32 %load1
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ret i32 %sel
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; CHECK: load i32, i32* %P1
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; CHECK: load i32, i32* %P1
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}
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define void @dse1(i32 *%P) {
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; CHECK-LABEL: @dse1
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; CHECK-NOT: store
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%v = load i32, i32* %P
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store i32 %v, i32* %P
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ret void
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}
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define void @dse2(i32 *%P) {
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; CHECK-LABEL: @dse2
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; CHECK-NOT: store
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%v = load atomic i32, i32* %P seq_cst, align 4
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store i32 %v, i32* %P
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ret void
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}
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define void @dse3(i32 *%P) {
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; CHECK-LABEL: @dse3
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; CHECK-NOT: store
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%v = load atomic i32, i32* %P seq_cst, align 4
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store atomic i32 %v, i32* %P unordered, align 4
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ret void
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}
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define i32 @dse4(i32 *%P, i32 *%Q) {
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; CHECK-LABEL: @dse4
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; CHECK-NOT: store
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; CHECK: ret i32 0
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%a = load i32, i32* %Q
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%v = load atomic i32, i32* %P unordered, align 4
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store atomic i32 %v, i32* %P unordered, align 4
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%b = load i32, i32* %Q
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%res = sub i32 %a, %b
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ret i32 %res
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}
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; Note that in this example, %P and %Q could in fact be the same
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; pointer. %v could be different than the value observed for %a
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; and that's okay because we're using relaxed memory ordering.
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; The only guarantee we have to provide is that each of the loads
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; has to observe some value written to that location. We do
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; not have to respect the order in which those writes were done.
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define i32 @dse5(i32 *%P, i32 *%Q) {
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; CHECK-LABEL: @dse5
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; CHECK-NOT: store
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; CHECK: ret i32 0
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%v = load atomic i32, i32* %P unordered, align 4
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%a = load atomic i32, i32* %Q unordered, align 4
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store atomic i32 %v, i32* %P unordered, align 4
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%b = load atomic i32, i32* %Q unordered, align 4
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%res = sub i32 %a, %b
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ret i32 %res
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}
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define void @dse_neg1(i32 *%P) {
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; CHECK-LABEL: @dse_neg1
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; CHECK: store
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%v = load i32, i32* %P
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store i32 5, i32* %P
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ret void
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}
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; Could remove the store, but only if ordering was somehow
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; encoded.
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define void @dse_neg2(i32 *%P) {
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; CHECK-LABEL: @dse_neg2
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; CHECK: store
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%v = load i32, i32* %P
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store atomic i32 %v, i32* %P seq_cst, align 4
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ret void
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}
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