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a2decca56b
We know that pcmp produces all-ones/all-zeros bitmasks, so we can use that behavior to avoid unnecessary constant loading. One could argue that load+and is actually a better solution for some CPUs (Intel big cores) because shifts don't have the same throughput potential as load+and on those cores, but that should be handled as a CPU-specific later transformation if it ever comes up. Removing the load is the more general x86 optimization. Note that the uneven usage of vpbroadcast in the test cases is filed as PR28505: https://llvm.org/bugs/show_bug.cgi?id=28505 Differential Revision: http://reviews.llvm.org/D22225 llvm-svn: 275276
46 lines
1.4 KiB
LLVM
46 lines
1.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: llc < %s -o - -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE
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; RUN: llc < %s -o - -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX
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define <8 x i16> @foo(<8 x i16> %a, <8 x i16> %b) {
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; SSE-LABEL: foo:
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; SSE: # BB#0:
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; SSE-NEXT: pcmpeqw %xmm1, %xmm0
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; SSE-NEXT: pand {{.*}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: foo:
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; AVX: # BB#0:
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; AVX-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: retq
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;
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%icmp = icmp eq <8 x i16> %a, %b
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%zext = zext <8 x i1> %icmp to <8 x i16>
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%shl = shl nuw nsw <8 x i16> %zext, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
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ret <8 x i16> %shl
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}
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; Don't fail with an assert due to an undef in the buildvector
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define <8 x i16> @bar(<8 x i16> %a, <8 x i16> %b) {
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; SSE-LABEL: bar:
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; SSE: # BB#0:
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; SSE-NEXT: pcmpeqw %xmm1, %xmm0
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; SSE-NEXT: psrlw $15, %xmm0
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; SSE-NEXT: psllw $5, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: bar:
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; AVX: # BB#0:
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; AVX-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vpsrlw $15, %xmm0, %xmm0
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; AVX-NEXT: vpsllw $5, %xmm0, %xmm0
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; AVX-NEXT: retq
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;
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%icmp = icmp eq <8 x i16> %a, %b
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%zext = zext <8 x i1> %icmp to <8 x i16>
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%shl = shl nuw nsw <8 x i16> %zext, <i16 5, i16 undef, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
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ret <8 x i16> %shl
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}
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