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llvm-mirror/test/CodeGen
Craig Topper c5e37509c1 [RISCV] Add add/sub saturation tests that exist on ARM/AArch64/X86
There have been some recent changes to the type legalization for
some of these intrinsics so I thought it would be good to have
coverage.
2021-02-16 11:19:57 -08:00
..
AArch64 Revert "[AArch64][GlobalISel] Fold constants into G_GLOBAL_VALUE" 2021-02-16 10:50:12 -08:00
AMDGPU [DAG] PromoteIntRes_ADDSUBSHLSAT - promote ISD::UADDSAT as clamped add 2021-02-16 17:37:44 +00:00
ARC
ARM [ARM] Extend search for increment in load/store optimizer 2021-02-15 13:17:21 +00:00
AVR [AVR] Fix a bug in 16-bit shifts 2021-02-14 11:54:55 +08:00
BPF
Generic
Hexagon
Inputs
Lanai
Mips
MIR
MSP430
NVPTX
PowerPC
RISCV [RISCV] Add add/sub saturation tests that exist on ARM/AArch64/X86 2021-02-16 11:19:57 -08:00
SPARC
SystemZ
Thumb
Thumb2 [ARM] Use rGPR for writeback vldrs 2021-02-16 16:44:47 +00:00
VE
WebAssembly [WebAssemblly] Fix rethrow's argument computation 2021-02-13 03:43:15 -08:00
WinCFGuard
WinEH
X86 [DAG] PromoteIntRes_ADDSUBSHLSAT - promote ISD::UADDSAT as clamped add 2021-02-16 17:37:44 +00:00
XCore