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4bf7d5872e
Upgrade of the IR text tests should be the only thing blocking making typed byval mandatory. Partially done through regex and partially manual.
35 lines
1.4 KiB
LLVM
35 lines
1.4 KiB
LLVM
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O1 < %s | FileCheck %s
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; This test verifies that the peephole optimization of address accesses
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; does not produce a load or store with a relocation that can't be
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; satisfied for a given instruction encoding. Reduced from a test supplied
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; by Hal Finkel.
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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%struct.S1 = type { [8 x i8] }
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@main.l_1554 = internal global { i8, i8, i8, i8, i8, i8, i8, i8 } { i8 -1, i8 -6, i8 57, i8 62, i8 -48, i8 0, i8 58, i8 80 }, align 1
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; Function Attrs: nounwind readonly
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define signext i32 @main() #0 {
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entry:
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%call = tail call fastcc signext i32 @func_90(%struct.S1* byval(%struct.S1) bitcast ({ i8, i8, i8, i8, i8, i8, i8, i8 }* @main.l_1554 to %struct.S1*))
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; CHECK-NOT: ld {{[0-9]+}}, main.l_1554@toc@l
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ret i32 %call
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}
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; Function Attrs: nounwind readonly
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define internal fastcc signext i32 @func_90(%struct.S1* byval(%struct.S1) nocapture %p_91) #0 {
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entry:
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%0 = bitcast %struct.S1* %p_91 to i64*
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%bf.load = load i64, i64* %0, align 1
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%bf.shl = shl i64 %bf.load, 26
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%bf.ashr = ashr i64 %bf.shl, 54
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%bf.cast = trunc i64 %bf.ashr to i32
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ret i32 %bf.cast
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}
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attributes #0 = { nounwind readonly "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
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