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e59e06d663
Current implementation of division estimation isn't correct for some cases like 1.0/0.0 (result is nan, not expected inf). And this change exposes a potential infinite loop: we use isConstOrConstSplatFP in combineRepeatedFPDivisors to look up if the divisor is some constant. But it doesn't work after legalized on some platforms. This patch restricts the method to act before LegalDAG. Reviewed By: spatel Differential Revision: https://reviews.llvm.org/D80542
51 lines
2.1 KiB
LLVM
51 lines
2.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-- < %s | FileCheck %s
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; Check if this causes infinite loop when estimation disabled
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define <4 x float> @repeated_fp_divisor_noest(float %a, <4 x float> %b) {
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; CHECK-LABEL: repeated_fp_divisor_noest:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xscvdpspn 0, 1
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; CHECK-NEXT: addis 3, 2, .LCPI0_1@toc@ha
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; CHECK-NEXT: addi 3, 3, .LCPI0_1@toc@l
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; CHECK-NEXT: lvx 3, 0, 3
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; CHECK-NEXT: addis 3, 2, .LCPI0_0@toc@ha
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; CHECK-NEXT: addi 3, 3, .LCPI0_0@toc@l
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; CHECK-NEXT: xxspltw 0, 0, 0
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; CHECK-NEXT: xvdivsp 0, 35, 0
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; CHECK-NEXT: lvx 3, 0, 3
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; CHECK-NEXT: xvmulsp 1, 34, 35
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; CHECK-NEXT: xvmulsp 34, 1, 0
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; CHECK-NEXT: blr
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%ins = insertelement <4 x float> undef, float %a, i32 0
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%splat = shufflevector <4 x float> %ins, <4 x float> undef, <4 x i32> zeroinitializer
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%t1 = fmul reassoc <4 x float> %b, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 0x3FF028F5C0000000>
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%mul = fdiv reassoc arcp nsz <4 x float> %t1, %splat
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ret <4 x float> %mul
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}
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define <4 x float> @repeated_fp_divisor(float %a, <4 x float> %b) {
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; CHECK-LABEL: repeated_fp_divisor:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xscvdpspn 0, 1
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; CHECK-NEXT: addis 3, 2, .LCPI1_0@toc@ha
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; CHECK-NEXT: addi 3, 3, .LCPI1_0@toc@l
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; CHECK-NEXT: lvx 3, 0, 3
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; CHECK-NEXT: addis 3, 2, .LCPI1_1@toc@ha
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; CHECK-NEXT: addi 3, 3, .LCPI1_1@toc@l
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; CHECK-NEXT: lvx 4, 0, 3
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; CHECK-NEXT: xxspltw 0, 0, 0
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; CHECK-NEXT: xvresp 1, 0
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; CHECK-NEXT: xvnmsubasp 35, 0, 1
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; CHECK-NEXT: xvmulsp 0, 34, 36
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; CHECK-NEXT: xvmaddasp 1, 1, 35
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; CHECK-NEXT: xvmulsp 34, 0, 1
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; CHECK-NEXT: blr
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%ins = insertelement <4 x float> undef, float %a, i32 0
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%splat = shufflevector <4 x float> %ins, <4 x float> undef, <4 x i32> zeroinitializer
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%t1 = fmul reassoc <4 x float> %b, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 0x3FF028F5C0000000>
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%mul = fdiv reassoc arcp nsz ninf <4 x float> %t1, %splat
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ret <4 x float> %mul
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}
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