1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 11:13:28 +01:00
llvm-mirror/test/CodeGen/PowerPC/spe-fastmath.ll
Justin Hibbits 14a0a3dcce PowerPC: Don't lower SELECT_CC to PPCISD::FSEL on SPE
SPE doesn't have a fsel instruction, so don't try to lower to it.

This fixes a "Cannot select: tN: f64 = PPCISD::FSEL tX, tY, tZ" error.

Reviewed By: #powerpc, lkail
Differential Revision: https://reviews.llvm.org/D77773
2020-07-31 22:52:47 -05:00

32 lines
1.0 KiB
LLVM

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu \
; RUN: -mattr=+spe | FileCheck %s
define void @no_fsel(i32 %e) #0 {
; CHECK-LABEL: no_fsel:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li 4, .LCPI0_0@l
; CHECK-NEXT: lis 5, .LCPI0_0@ha
; CHECK-NEXT: evlddx 4, 5, 4
; CHECK-NEXT: efdcfui 3, 3
; CHECK-NEXT: efdmul 5, 3, 3
; CHECK-NEXT: efdcmpeq 0, 5, 4
; CHECK-NEXT: ble 0, .LBB0_2
; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: evor 3, 4, 4
; CHECK-NEXT: .LBB0_2: # %entry
; CHECK-NEXT: efdctsiz 3, 3
; CHECK-NEXT: sth 3, 0(3)
; CHECK-NEXT: blr
entry:
%conv = uitofp i32 %e to double
%mul = fmul double %conv, %conv
%tobool = fcmp une double %mul, 0.000000e+00
%cond = select i1 %tobool, double %conv, double 0.000000e+00
%conv3 = fptosi double %cond to i16
store i16 %conv3, i16* undef
ret void
}
attributes #0 = { "no-infs-fp-math"="true" "no-nans-fp-math"="true" }