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53516796c3
This is an optimized approach for D94155. Previous code build the model that tile config register is the user of each AMX instruction. There is a problem for the tile config register spill. When across function, the ldtilecfg instruction may be inserted on each AMX instruction which use tile config register. This cause all tile data register clobber. To fix this issue, we remove the model of tile config register. Instead, we analyze the AMX instructions between one call to another. We will insert ldtilecfg after the first call if we find any AMX instructions. Reviewed By: LuoYuanke Differential Revision: https://reviews.llvm.org/D95136
15 lines
501 B
LLVM
15 lines
501 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+amx-tile -mattr=+amx-bf16 -verify-machineinstrs | FileCheck %s
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define void @test_amx() {
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; CHECK-LABEL: test_amx:
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; CHECK: # %bb.0:
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; CHECK-NEXT: tdpbf16ps %tmm7, %tmm4, %tmm3
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; CHECK-NEXT: tilerelease
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; CHECK-NEXT: retq
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call void @llvm.x86.tdpbf16ps(i8 3, i8 4, i8 7)
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ret void
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}
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declare void @llvm.x86.tdpbf16ps(i8 %tile0, i8 %tile1, i8 %tile2)
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