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6019f1db6d
This removes everything but int_x86_avx512_mask_vcvtph2ps_512 which provides the SAE variant, but even this can use the fpext generic if the rounding control is the default. Differential Revision: https://reviews.llvm.org/D75162
117 lines
4.5 KiB
LLVM
117 lines
4.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -fast-isel -mtriple=i386-unknown-unknown -mattr=+avx,+f16c | FileCheck %s --check-prefixes=CHECK,X86
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; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+avx,+f16c | FileCheck %s --check-prefixes=CHECK,X64
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; NOTE: This should use IR equivalent to what is generated by clang/test/CodeGen/f16c-builtins.c
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define float @test_cvtsh_ss(i16 %a0) nounwind {
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; X86-LABEL: test_cvtsh_ss:
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; X86: # %bb.0:
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; X86-NEXT: pushl %eax
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; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: vmovd %eax, %xmm0
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; X86-NEXT: vcvtph2ps %xmm0, %xmm0
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; X86-NEXT: vmovss %xmm0, (%esp)
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; X86-NEXT: flds (%esp)
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; X86-NEXT: popl %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: test_cvtsh_ss:
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; X64: # %bb.0:
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; X64-NEXT: movzwl %di, %eax
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; X64-NEXT: vmovd %eax, %xmm0
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; X64-NEXT: vcvtph2ps %xmm0, %xmm0
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; X64-NEXT: retq
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%ins0 = insertelement <8 x i16> undef, i16 %a0, i32 0
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%ins1 = insertelement <8 x i16> %ins0, i16 0, i32 1
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%ins2 = insertelement <8 x i16> %ins1, i16 0, i32 2
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%ins3 = insertelement <8 x i16> %ins2, i16 0, i32 3
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%ins4 = insertelement <8 x i16> %ins3, i16 0, i32 4
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%ins5 = insertelement <8 x i16> %ins4, i16 0, i32 5
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%ins6 = insertelement <8 x i16> %ins5, i16 0, i32 6
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%ins7 = insertelement <8 x i16> %ins6, i16 0, i32 7
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%shuffle = shufflevector <8 x i16> %ins7, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%bc = bitcast <4 x i16> %shuffle to <4 x half>
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%cvt = fpext <4 x half> %bc to <4 x float>
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%res = extractelement <4 x float> %cvt, i32 0
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ret float %res
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}
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define i16 @test_cvtss_sh(float %a0) nounwind {
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; X86-LABEL: test_cvtss_sh:
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; X86: # %bb.0:
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; X86-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; X86-NEXT: vxorps %xmm1, %xmm1, %xmm1
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; X86-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
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; X86-NEXT: vcvtps2ph $0, %xmm0, %xmm0
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; X86-NEXT: vmovd %xmm0, %eax
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; X86-NEXT: # kill: def $ax killed $ax killed $eax
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; X86-NEXT: retl
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;
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; X64-LABEL: test_cvtss_sh:
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; X64: # %bb.0:
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; X64-NEXT: vxorps %xmm1, %xmm1, %xmm1
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; X64-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
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; X64-NEXT: vcvtps2ph $0, %xmm0, %xmm0
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; X64-NEXT: vmovd %xmm0, %eax
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; X64-NEXT: # kill: def $ax killed $ax killed $eax
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; X64-NEXT: retq
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%ins0 = insertelement <4 x float> undef, float %a0, i32 0
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%ins1 = insertelement <4 x float> %ins0, float 0.000000e+00, i32 1
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%ins2 = insertelement <4 x float> %ins1, float 0.000000e+00, i32 2
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%ins3 = insertelement <4 x float> %ins2, float 0.000000e+00, i32 3
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%cvt = call <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float> %ins3, i32 0)
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%res = extractelement <8 x i16> %cvt, i32 0
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ret i16 %res
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}
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define <4 x float> @test_mm_cvtph_ps(<2 x i64> %a0) nounwind {
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; CHECK-LABEL: test_mm_cvtph_ps:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vcvtph2ps %xmm0, %xmm0
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; CHECK-NEXT: ret{{[l|q]}}
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%arg0 = bitcast <2 x i64> %a0 to <8 x i16>
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%shuffle = shufflevector <8 x i16> %arg0, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%bc = bitcast <4 x i16> %shuffle to <4 x half>
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%res = fpext <4 x half> %bc to <4 x float>
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ret <4 x float> %res
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}
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define <8 x float> @test_mm256_cvtph_ps(<2 x i64> %a0) nounwind {
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; CHECK-LABEL: test_mm256_cvtph_ps:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vcvtph2ps %xmm0, %ymm0
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; CHECK-NEXT: ret{{[l|q]}}
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%arg0 = bitcast <2 x i64> %a0 to <8 x i16>
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%bc = bitcast <8 x i16> %arg0 to <8 x half>
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%res = fpext <8 x half> %bc to <8 x float>
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ret <8 x float> %res
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}
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define <2 x i64> @test_mm_cvtps_ph(<4 x float> %a0) nounwind {
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; CHECK-LABEL: test_mm_cvtps_ph:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vcvtps2ph $0, %xmm0, %xmm0
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; CHECK-NEXT: ret{{[l|q]}}
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%cvt = call <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float> %a0, i32 0)
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%res = bitcast <8 x i16> %cvt to <2 x i64>
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ret <2 x i64> %res
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}
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define <2 x i64> @test_mm256_cvtps_ph(<8 x float> %a0) nounwind {
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; CHECK-LABEL: test_mm256_cvtps_ph:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vcvtps2ph $0, %ymm0, %xmm0
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: ret{{[l|q]}}
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%cvt = call <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float> %a0, i32 0)
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%res = bitcast <8 x i16> %cvt to <2 x i64>
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ret <2 x i64> %res
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}
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declare <4 x float> @llvm.x86.vcvtph2ps.128(<8 x i16>) nounwind readonly
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declare <8 x float> @llvm.x86.vcvtph2ps.256(<8 x i16>) nounwind readonly
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declare <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float>, i32) nounwind readonly
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declare <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float>, i32) nounwind readonly
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