Hrvoje Varga 52c95ef5b8 [mips][micromips] Implement LD, LLD, LWU, SD, DSRL, DSRL32 and DSRLV instructions ... Differential Revision: http://reviews.llvm.org/D16625 llvm-svn: 273850		2016-06-27 08:23:28 +00:00
..
AArch64	AArch64: allow MOV (imm) alias to be printed	2016-06-16 01:42:25 +00:00
AMDGPU	[AMDGPU] Disassembler: Support for sdwa instructions	2016-06-09 11:04:45 +00:00
ARM	RAS extensions are part of ARMv8.2-A. This change enables them by introducing a	2016-06-03 14:03:27 +00:00
Hexagon	[Hexagon] Treat all conditional branches as predicted (not-taken by default)	2016-05-09 18:22:07 +00:00
Lanai	[lanai] Add Lanai backend.	2016-03-28 13:09:54 +00:00
Mips	[mips][micromips] Implement LD, LLD, LWU, SD, DSRL, DSRL32 and DSRLV instructions	2016-06-27 08:23:28 +00:00
PowerPC	This reverts commit r265505.	2016-04-28 20:00:42 +00:00
Sparc	This change adds co-processor condition branching and conditional traps to the Sparc back-end.	2016-03-09 18:20:21 +00:00
SystemZ	[SystemZ] Support Compare and Traps	2016-06-10 19:58:10 +00:00
X86	Add new flag and intrinsic support for MWAITX and MONITORX instructions	2016-05-18 11:59:12 +00:00
XCore	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00