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907a18645b
Someone couldn't bear to have a completely orthogonal set of floating-point registers, so we've got some instructions that only accept v0-v15 (coming in ARMv9, V128_prime: you're allowed v2, v3, v5, v7, ...). Anyway, we were permitting even the out of range registers during assembly (CodeGen handled it correctly). This adds a diagnostic. llvm-svn: 207412
12 lines
357 B
ArmAsm
12 lines
357 B
ArmAsm
// RUN: not llvm-mc -triple arm64 -mattr=neon %s 2> %t > /dev/null
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// RUN: FileCheck %s < %t
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sqrdmulh v0.8h, v1.8h, v16.h[0]
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// CHECK: error: invalid operand for instruction
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sqrdmulh h0, h1, v16.h[0]
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// CHECK: error: invalid operand for instruction
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sqdmull2 v0.4h, v1.8h, v16.h[0]
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// CHECK: error: invalid operand for instruction
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