mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-23 21:13:02 +02:00
39b5a7c2bb
Summary: Adds a RegisterBank tablegen class that can be used to declare the register banks and an associated tablegen pass to generate the necessary code. Changes since first commit attempt: * Added missing guards * Added more missing guards * Found and fixed a use-after-free bug involving Twine locals Reviewers: t.p.northover, ab, rovka, qcolombet Reviewed By: qcolombet Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka Differential Revision: https://reviews.llvm.org/D27338 llvm-svn: 292478
21 lines
693 B
TableGen
21 lines
693 B
TableGen
//=- AArch64RegisterBank.td - Describe the AArch64 Banks -----*- tablegen -*-=//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// General Purpose Registers: W, X.
|
|
def GPRRegBank : RegisterBank<"GPR", [GPR64all]>;
|
|
|
|
/// Floating Point/Vector Registers: B, H, S, D, Q.
|
|
def FPRRegBank : RegisterBank<"FPR", [QQQQ]>;
|
|
|
|
/// Conditional register: NZCV.
|
|
def CCRRegBank : RegisterBank<"CCR", [CCR]>;
|