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eb66b33867
I did this a long time ago with a janky python script, but now clang-format has built-in support for this. I fed clang-format every line with a #include and let it re-sort things according to the precise LLVM rules for include ordering baked into clang-format these days. I've reverted a number of files where the results of sorting includes isn't healthy. Either places where we have legacy code relying on particular include ordering (where possible, I'll fix these separately) or where we have particular formatting around #include lines that I didn't want to disturb in this patch. This patch is *entirely* mechanical. If you get merge conflicts or anything, just ignore the changes in this patch and run clang-format over your #include lines in the files. Sorry for any noise here, but it is important to keep these things stable. I was seeing an increasing number of patches with irrelevant re-ordering of #include lines because clang-format was used. This patch at least isolates that churn, makes it easy to skip when resolving conflicts, and gets us to a clean baseline (again). llvm-svn: 304787
128 lines
3.9 KiB
C++
128 lines
3.9 KiB
C++
//===-- BPFRegisterInfo.cpp - BPF Register Information ----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the BPF implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "BPFRegisterInfo.h"
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#include "BPF.h"
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#include "BPFSubtarget.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/IR/DiagnosticInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Target/TargetFrameLowering.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#define GET_REGINFO_TARGET_DESC
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#include "BPFGenRegisterInfo.inc"
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using namespace llvm;
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BPFRegisterInfo::BPFRegisterInfo()
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: BPFGenRegisterInfo(BPF::R0) {}
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const MCPhysReg *
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BPFRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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return CSR_SaveList;
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}
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BitVector BPFRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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Reserved.set(BPF::R10); // R10 is read only frame pointer
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Reserved.set(BPF::R11); // R11 is pseudo stack pointer
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return Reserved;
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}
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static void WarnSize(int Offset, MachineFunction &MF, DebugLoc& DL)
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{
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if (Offset <= -512) {
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auto F = MF.getFunction();
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DiagnosticInfoUnsupported DiagStackSize(*F,
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"Looks like the BPF stack limit of 512 bytes is exceeded. "
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"Please move large on stack variables into BPF per-cpu array map.\n",
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DL);
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F->getContext().diagnose(DiagStackSize);
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}
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}
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void BPFRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, unsigned FIOperandNum,
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RegScavenger *RS) const {
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assert(SPAdj == 0 && "Unexpected");
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unsigned i = 0;
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MachineInstr &MI = *II;
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MachineBasicBlock &MBB = *MI.getParent();
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MachineFunction &MF = *MBB.getParent();
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DebugLoc DL = MI.getDebugLoc();
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if (!DL)
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/* try harder to get some debug loc */
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for (auto &I : MBB)
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if (I.getDebugLoc()) {
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DL = I.getDebugLoc();
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break;
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}
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while (!MI.getOperand(i).isFI()) {
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++i;
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assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
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}
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unsigned FrameReg = getFrameRegister(MF);
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int FrameIndex = MI.getOperand(i).getIndex();
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const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
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if (MI.getOpcode() == BPF::MOV_rr) {
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int Offset = MF.getFrameInfo().getObjectOffset(FrameIndex);
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WarnSize(Offset, MF, DL);
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MI.getOperand(i).ChangeToRegister(FrameReg, false);
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unsigned reg = MI.getOperand(i - 1).getReg();
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BuildMI(MBB, ++II, DL, TII.get(BPF::ADD_ri), reg)
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.addReg(reg)
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.addImm(Offset);
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return;
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}
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int Offset = MF.getFrameInfo().getObjectOffset(FrameIndex) +
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MI.getOperand(i + 1).getImm();
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if (!isInt<32>(Offset))
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llvm_unreachable("bug in frame offset");
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WarnSize(Offset, MF, DL);
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if (MI.getOpcode() == BPF::FI_ri) {
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// architecture does not really support FI_ri, replace it with
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// MOV_rr <target_reg>, frame_reg
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// ADD_ri <target_reg>, imm
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unsigned reg = MI.getOperand(i - 1).getReg();
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BuildMI(MBB, ++II, DL, TII.get(BPF::MOV_rr), reg)
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.addReg(FrameReg);
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BuildMI(MBB, II, DL, TII.get(BPF::ADD_ri), reg)
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.addReg(reg)
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.addImm(Offset);
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// Remove FI_ri instruction
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MI.eraseFromParent();
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} else {
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MI.getOperand(i).ChangeToRegister(FrameReg, false);
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MI.getOperand(i + 1).ChangeToImmediate(Offset);
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}
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}
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unsigned BPFRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
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return BPF::R10;
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}
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