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9c8fac17d3
We don't have PMCs to cover many of the Jaguar resources but we can at least monitor the FPU issue pipes which give an indication of the fpu uop count, just not the execution resources. llvm-svn: 336089
78 lines
4.2 KiB
TableGen
78 lines
4.2 KiB
TableGen
//===-- X86PfmCounters.td - X86 Hardware Counters ----------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This describes the available hardware counters for various subtargets.
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//
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//===----------------------------------------------------------------------===//
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let SchedModel = SandyBridgeModel in {
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def SBCycleCounter : PfmCycleCounter<"unhalted_core_cycles">;
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def SBPort0Counter : PfmIssueCounter<SBPort0, ["uops_dispatched_port:port_0"]>;
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def SBPort1Counter : PfmIssueCounter<SBPort1, ["uops_dispatched_port:port_1"]>;
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def SBPort23Counter : PfmIssueCounter<SBPort23,
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["uops_dispatched_port:port_2",
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"uops_dispatched_port:port_3"]>;
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def SBPort4Counter : PfmIssueCounter<SBPort4, ["uops_dispatched_port:port_4"]>;
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def SBPort5Counter : PfmIssueCounter<SBPort5, ["uops_dispatched_port:port_5"]>;
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}
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let SchedModel = HaswellModel in {
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def HWCycleCounter : PfmCycleCounter<"unhalted_core_cycles">;
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def HWPort0Counter : PfmIssueCounter<HWPort0, ["uops_dispatched_port:port_0"]>;
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def HWPort1Counter : PfmIssueCounter<HWPort1, ["uops_dispatched_port:port_1"]>;
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def HWPort2Counter : PfmIssueCounter<HWPort2, ["uops_dispatched_port:port_2"]>;
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def HWPort3Counter : PfmIssueCounter<HWPort3, ["uops_dispatched_port:port_3"]>;
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def HWPort4Counter : PfmIssueCounter<HWPort4, ["uops_dispatched_port:port_4"]>;
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def HWPort5Counter : PfmIssueCounter<HWPort5, ["uops_dispatched_port:port_5"]>;
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def HWPort6Counter : PfmIssueCounter<HWPort6, ["uops_dispatched_port:port_6"]>;
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def HWPort7Counter : PfmIssueCounter<HWPort7, ["uops_dispatched_port:port_7"]>;
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}
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let SchedModel = BroadwellModel in {
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def BWCycleCounter : PfmCycleCounter<"unhalted_core_cycles">;
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def BWPort0Counter : PfmIssueCounter<BWPort0, ["uops_executed_port:port_0"]>;
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def BWPort1Counter : PfmIssueCounter<BWPort1, ["uops_executed_port:port_1"]>;
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def BWPort2Counter : PfmIssueCounter<BWPort2, ["uops_executed_port:port_2"]>;
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def BWPort3Counter : PfmIssueCounter<BWPort3, ["uops_executed_port:port_3"]>;
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def BWPort4Counter : PfmIssueCounter<BWPort4, ["uops_executed_port:port_4"]>;
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def BWPort5Counter : PfmIssueCounter<BWPort5, ["uops_executed_port:port_5"]>;
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def BWPort6Counter : PfmIssueCounter<BWPort6, ["uops_executed_port:port_6"]>;
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def BWPort7Counter : PfmIssueCounter<BWPort7, ["uops_executed_port:port_7"]>;
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}
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let SchedModel = SkylakeClientModel in {
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def SKLCycleCounter : PfmCycleCounter<"unhalted_core_cycles">;
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def SKLPort0Counter : PfmIssueCounter<SKLPort0, ["uops_dispatched_port:port_0"]>;
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def SKLPort1Counter : PfmIssueCounter<SKLPort1, ["uops_dispatched_port:port_1"]>;
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def SKLPort2Counter : PfmIssueCounter<SKLPort2, ["uops_dispatched_port:port_2"]>;
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def SKLPort3Counter : PfmIssueCounter<SKLPort3, ["uops_dispatched_port:port_3"]>;
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def SKLPort4Counter : PfmIssueCounter<SKLPort4, ["uops_dispatched_port:port_4"]>;
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def SKLPort5Counter : PfmIssueCounter<SKLPort5, ["uops_dispatched_port:port_5"]>;
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def SKLPort6Counter : PfmIssueCounter<SKLPort6, ["uops_dispatched_port:port_6"]>;
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def SKLPort7Counter : PfmIssueCounter<SKLPort7, ["uops_dispatched_port:port_7"]>;
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}
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let SchedModel = SkylakeServerModel in {
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def SKXCycleCounter : PfmCycleCounter<"unhalted_core_cycles">;
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def SKXPort0Counter : PfmIssueCounter<SKXPort0, ["uops_dispatched_port:port_0"]>;
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def SKXPort1Counter : PfmIssueCounter<SKXPort1, ["uops_dispatched_port:port_1"]>;
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def SKXPort2Counter : PfmIssueCounter<SKXPort2, ["uops_dispatched_port:port_2"]>;
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def SKXPort3Counter : PfmIssueCounter<SKXPort3, ["uops_dispatched_port:port_3"]>;
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def SKXPort4Counter : PfmIssueCounter<SKXPort4, ["uops_dispatched_port:port_4"]>;
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def SKXPort5Counter : PfmIssueCounter<SKXPort5, ["uops_dispatched_port:port_5"]>;
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def SKXPort6Counter : PfmIssueCounter<SKXPort6, ["uops_dispatched_port:port_6"]>;
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def SKXPort7Counter : PfmIssueCounter<SKXPort7, ["uops_dispatched_port:port_7"]>;
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}
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let SchedModel = BtVer2Model in {
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def JCycleCounter : PfmCycleCounter<"cpu_clk_unhalted">;
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def JFPU0Counter : PfmIssueCounter<JFPU0, ["dispatched_fpu:pipe0"]>;
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def JFPU1Counter : PfmIssueCounter<JFPU1, ["dispatched_fpu:pipe1"]>;
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}
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