mirror of
https://github.com/RPCS3/llvm-mirror.git
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db6cd30745
Summary:
{F6603964}
While there is still some discrepancies within that new group,
it is clearly separate from the other shifts.
And Agner's tables agree, these double shifts are clearly
different from the normal shifts/rotates.
I'm guessing `FeatureSlowSHLD` is related.
Indeed, a basic sched pair is *not* the /best/ match.
But keeping it in the WriteShift is /clearly/ not ideal either.
This can and likely will be fine-tuned later.
This is purely mechanical change, it does not change any numbers,
as the [lack of the change of] mca tests show.
Reviewers: craig.topper, RKSimon, andreadb
Reviewed By: craig.topper
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D49015
llvm-svn: 336515
661 lines
32 KiB
TableGen
661 lines
32 KiB
TableGen
//=- X86ScheduleBtVer2.td - X86 BtVer2 (Jaguar) Scheduling ---*- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the machine model for AMD btver2 (Jaguar) to support
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// instruction scheduling and other instruction cost heuristics. Based off AMD Software
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// Optimization Guide for AMD Family 16h Processors & Instruction Latency appendix.
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//
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//===----------------------------------------------------------------------===//
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def BtVer2Model : SchedMachineModel {
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// All x86 instructions are modeled as a single micro-op, and btver2 can
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// decode 2 instructions per cycle.
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let IssueWidth = 2;
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let MicroOpBufferSize = 64; // Retire Control Unit
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let LoadLatency = 5; // FPU latency (worse case cf Integer 3 cycle latency)
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let HighLatency = 25;
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let MispredictPenalty = 14; // Minimum branch misdirection penalty
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let PostRAScheduler = 1;
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// FIXME: SSE4/AVX is unimplemented. This flag is set to allow
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// the scheduler to assign a default model to unrecognized opcodes.
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let CompleteModel = 0;
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}
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let SchedModel = BtVer2Model in {
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// Jaguar can issue up to 6 micro-ops in one cycle
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def JALU0 : ProcResource<1>; // Integer Pipe0: integer ALU0 (also handle FP->INT jam)
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def JALU1 : ProcResource<1>; // Integer Pipe1: integer ALU1/MUL/DIV
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def JLAGU : ProcResource<1>; // Integer Pipe2: LAGU
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def JSAGU : ProcResource<1>; // Integer Pipe3: SAGU (also handles 3-operand LEA)
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def JFPU0 : ProcResource<1>; // Vector/FPU Pipe0: VALU0/VIMUL/FPA
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def JFPU1 : ProcResource<1>; // Vector/FPU Pipe1: VALU1/STC/FPM
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// The Integer PRF for Jaguar is 64 entries, and it holds the architectural and
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// speculative version of the 64-bit integer registers.
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// Reference: www.realworldtech.com/jaguar/4/
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def JIntegerPRF : RegisterFile<64, [GR8, GR16, GR32, GR64, CCR]>;
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// The Jaguar FP Retire Queue renames SIMD and FP uOps onto a pool of 72 SSE
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// registers. Operations on 256-bit data types are cracked into two COPs.
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// Reference: www.realworldtech.com/jaguar/4/
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def JFpuPRF: RegisterFile<72, [VR64, VR128, VR256], [1, 1, 2]>;
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// The retire control unit (RCU) can track up to 64 macro-ops in-flight. It can
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// retire up to two macro-ops per cycle.
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// Reference: "Software Optimization Guide for AMD Family 16h Processors"
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def JRCU : RetireControlUnit<64, 2>;
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// Integer Pipe Scheduler
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def JALU01 : ProcResGroup<[JALU0, JALU1]> {
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let BufferSize=20;
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}
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// AGU Pipe Scheduler
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def JLSAGU : ProcResGroup<[JLAGU, JSAGU]> {
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let BufferSize=12;
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}
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// Fpu Pipe Scheduler
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def JFPU01 : ProcResGroup<[JFPU0, JFPU1]> {
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let BufferSize=18;
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}
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// Functional units
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def JDiv : ProcResource<1>; // integer division
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def JMul : ProcResource<1>; // integer multiplication
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def JVALU0 : ProcResource<1>; // vector integer
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def JVALU1 : ProcResource<1>; // vector integer
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def JVIMUL : ProcResource<1>; // vector integer multiplication
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def JSTC : ProcResource<1>; // vector store/convert
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def JFPM : ProcResource<1>; // FP multiplication
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def JFPA : ProcResource<1>; // FP addition
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// Functional unit groups
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def JFPX : ProcResGroup<[JFPA, JFPM]>;
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def JVALU : ProcResGroup<[JVALU0, JVALU1]>;
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// Integer loads are 3 cycles, so ReadAfterLd registers needn't be available until 3
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// cycles after the memory operand.
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def : ReadAdvance<ReadAfterLd, 3>;
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// Many SchedWrites are defined in pairs with and without a folded load.
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// Instructions with folded loads are usually micro-fused, so they only appear
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// as two micro-ops when dispatched by the schedulers.
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// This multiclass defines the resource usage for variants with and without
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// folded loads.
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multiclass JWriteResIntPair<X86FoldableSchedWrite SchedRW,
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list<ProcResourceKind> ExePorts,
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int Lat, list<int> Res = [], int UOps = 1> {
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// Register variant is using a single cycle on ExePort.
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def : WriteRes<SchedRW, ExePorts> {
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let Latency = Lat;
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let ResourceCycles = Res;
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let NumMicroOps = UOps;
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}
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// Memory variant also uses a cycle on JLAGU and adds 3 cycles to the
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// latency.
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def : WriteRes<SchedRW.Folded, !listconcat([JLAGU], ExePorts)> {
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let Latency = !add(Lat, 3);
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let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res));
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let NumMicroOps = UOps;
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}
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}
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multiclass JWriteResFpuPair<X86FoldableSchedWrite SchedRW,
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list<ProcResourceKind> ExePorts,
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int Lat, list<int> Res = [], int UOps = 1> {
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// Register variant is using a single cycle on ExePort.
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def : WriteRes<SchedRW, ExePorts> {
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let Latency = Lat;
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let ResourceCycles = Res;
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let NumMicroOps = UOps;
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}
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// Memory variant also uses a cycle on JLAGU and adds 5 cycles to the
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// latency.
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def : WriteRes<SchedRW.Folded, !listconcat([JLAGU], ExePorts)> {
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let Latency = !add(Lat, 5);
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let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res));
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let NumMicroOps = UOps;
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}
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}
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multiclass JWriteResYMMPair<X86FoldableSchedWrite SchedRW,
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list<ProcResourceKind> ExePorts,
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int Lat, list<int> Res = [2], int UOps = 2> {
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// Register variant is using a single cycle on ExePort.
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def : WriteRes<SchedRW, ExePorts> {
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let Latency = Lat;
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let ResourceCycles = Res;
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let NumMicroOps = UOps;
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}
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// Memory variant also uses 2 cycles on JLAGU and adds 5 cycles to the
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// latency.
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def : WriteRes<SchedRW.Folded, !listconcat([JLAGU], ExePorts)> {
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let Latency = !add(Lat, 5);
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let ResourceCycles = !listconcat([2], Res);
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let NumMicroOps = UOps;
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}
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}
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// A folded store needs a cycle on the SAGU for the store data.
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def : WriteRes<WriteRMW, [JSAGU]>;
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////////////////////////////////////////////////////////////////////////////////
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// Arithmetic.
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////////////////////////////////////////////////////////////////////////////////
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defm : JWriteResIntPair<WriteALU, [JALU01], 1>;
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defm : JWriteResIntPair<WriteADC, [JALU01], 1, [2]>;
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defm : JWriteResIntPair<WriteIMul, [JALU1, JMul], 3, [1, 1], 2>; // i8/i16/i32 multiplication
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defm : JWriteResIntPair<WriteIMul64, [JALU1, JMul], 6, [1, 4], 2>; // i64 multiplication
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defm : X86WriteRes<WriteIMulH, [JALU1], 6, [4], 1>;
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defm : JWriteResIntPair<WriteDiv8, [JALU1, JDiv], 12, [1, 12], 1>;
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defm : JWriteResIntPair<WriteDiv16, [JALU1, JDiv], 17, [1, 17], 2>;
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defm : JWriteResIntPair<WriteDiv32, [JALU1, JDiv], 25, [1, 25], 2>;
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defm : JWriteResIntPair<WriteDiv64, [JALU1, JDiv], 41, [1, 41], 2>;
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defm : JWriteResIntPair<WriteIDiv8, [JALU1, JDiv], 12, [1, 12], 1>;
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defm : JWriteResIntPair<WriteIDiv16, [JALU1, JDiv], 17, [1, 17], 2>;
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defm : JWriteResIntPair<WriteIDiv32, [JALU1, JDiv], 25, [1, 25], 2>;
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defm : JWriteResIntPair<WriteIDiv64, [JALU1, JDiv], 41, [1, 41], 2>;
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defm : JWriteResIntPair<WriteCRC32, [JALU01], 3, [4], 3>;
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defm : JWriteResIntPair<WriteCMOV, [JALU01], 1>; // Conditional move.
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defm : JWriteResIntPair<WriteCMOV2, [JALU01], 1>; // Conditional (CF + ZF flag) move.
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defm : X86WriteRes<WriteFCMOV, [JFPU0, JFPA], 3, [1,1], 1>; // x87 conditional move.
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def : WriteRes<WriteSETCC, [JALU01]>; // Setcc.
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def : WriteRes<WriteSETCCStore, [JALU01,JSAGU]>;
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def : WriteRes<WriteLAHFSAHF, [JALU01]>;
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// This is for simple LEAs with one or two input operands.
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// FIXME: SAGU 3-operand LEA
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def : WriteRes<WriteLEA, [JALU01]>;
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// Bit counts.
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defm : JWriteResIntPair<WriteBSF, [JALU01], 5, [4], 8>;
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defm : JWriteResIntPair<WriteBSR, [JALU01], 5, [4], 8>;
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defm : JWriteResIntPair<WritePOPCNT, [JALU01], 1>;
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defm : JWriteResIntPair<WriteLZCNT, [JALU01], 1>;
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defm : JWriteResIntPair<WriteTZCNT, [JALU01], 2, [2]>;
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// BMI1 BEXTR, BMI2 BZHI
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defm : JWriteResIntPair<WriteBEXTR, [JALU01], 1>;
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defm : X86WriteResPairUnsupported<WriteBZHI>;
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////////////////////////////////////////////////////////////////////////////////
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// Integer shifts and rotates.
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////////////////////////////////////////////////////////////////////////////////
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defm : JWriteResIntPair<WriteShift, [JALU01], 1>;
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defm : JWriteResIntPair<WriteShiftDouble, [JALU01], 1>;
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def JWriteSHLDrri : SchedWriteRes<[JALU01]> {
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let Latency = 3;
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let ResourceCycles = [6];
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let NumMicroOps = 6;
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}
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def: InstRW<[JWriteSHLDrri], (instrs SHLD16rri8, SHLD32rri8, SHLD64rri8,
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SHRD16rri8, SHRD32rri8, SHRD64rri8)>;
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def JWriteSHLDrrCL : SchedWriteRes<[JALU01]> {
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let Latency = 4;
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let ResourceCycles = [8];
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let NumMicroOps = 7;
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}
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def: InstRW<[JWriteSHLDrrCL], (instrs SHLD16rrCL, SHLD32rrCL, SHLD64rrCL,
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SHRD16rrCL, SHRD32rrCL, SHRD64rrCL)>;
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def JWriteSHLDm : SchedWriteRes<[JLAGU, JALU01]> {
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let Latency = 9;
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let ResourceCycles = [1, 22];
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let NumMicroOps = 8;
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}
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def: InstRW<[JWriteSHLDm],(instrs SHLD16mri8, SHLD32mri8, SHLD64mri8,
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SHLD16mrCL, SHLD32mrCL, SHLD64mrCL,
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SHRD16mri8, SHRD32mri8, SHRD64mri8,
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SHRD16mrCL, SHRD32mrCL, SHRD64mrCL)>;
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////////////////////////////////////////////////////////////////////////////////
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// Loads, stores, and moves, not folded with other operations.
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////////////////////////////////////////////////////////////////////////////////
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def : WriteRes<WriteLoad, [JLAGU]> { let Latency = 5; }
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def : WriteRes<WriteStore, [JSAGU]>;
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def : WriteRes<WriteStoreNT, [JSAGU]>;
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def : WriteRes<WriteMove, [JALU01]>;
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// Load/store MXCSR.
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// FIXME: These are copy and pasted from WriteLoad/Store.
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def : WriteRes<WriteLDMXCSR, [JLAGU]> { let Latency = 5; }
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def : WriteRes<WriteSTMXCSR, [JSAGU]>;
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// Treat misc copies as a move.
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def : InstRW<[WriteMove], (instrs COPY)>;
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////////////////////////////////////////////////////////////////////////////////
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// Idioms that clear a register, like xorps %xmm0, %xmm0.
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// These can often bypass execution ports completely.
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////////////////////////////////////////////////////////////////////////////////
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def : WriteRes<WriteZero, []>;
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////////////////////////////////////////////////////////////////////////////////
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// Branches don't produce values, so they have no latency, but they still
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// consume resources. Indirect branches can fold loads.
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////////////////////////////////////////////////////////////////////////////////
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defm : JWriteResIntPair<WriteJump, [JALU01], 1>;
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////////////////////////////////////////////////////////////////////////////////
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// Special case scheduling classes.
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////////////////////////////////////////////////////////////////////////////////
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def : WriteRes<WriteSystem, [JALU01]> { let Latency = 100; }
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def : WriteRes<WriteMicrocoded, [JALU01]> { let Latency = 100; }
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def : WriteRes<WriteFence, [JSAGU]>;
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// Nops don't have dependencies, so there's no actual latency, but we set this
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// to '1' to tell the scheduler that the nop uses an ALU slot for a cycle.
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def : WriteRes<WriteNop, [JALU01]> { let Latency = 1; }
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////////////////////////////////////////////////////////////////////////////////
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// Floating point. This covers both scalar and vector operations.
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////////////////////////////////////////////////////////////////////////////////
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defm : X86WriteRes<WriteFLD0, [JFPU1, JSTC], 3, [1,1], 1>;
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defm : X86WriteRes<WriteFLD1, [JFPU1, JSTC], 3, [1,1], 1>;
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defm : X86WriteRes<WriteFLDC, [JFPU1, JSTC], 3, [1,1], 1>;
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defm : X86WriteRes<WriteFLoad, [JLAGU, JFPU01, JFPX], 5, [1, 1, 1], 1>;
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defm : X86WriteRes<WriteFLoadX, [JLAGU, JFPU01, JFPX], 5, [1, 1, 1], 1>;
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defm : X86WriteRes<WriteFLoadY, [JLAGU, JFPU01, JFPX], 5, [1, 1, 1], 1>;
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defm : X86WriteRes<WriteFMaskedLoad, [JLAGU, JFPU01, JFPX], 6, [1, 1, 2], 1>;
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defm : X86WriteRes<WriteFMaskedLoadY, [JLAGU, JFPU01, JFPX], 6, [2, 2, 4], 2>;
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defm : X86WriteRes<WriteFStore, [JSAGU, JFPU1, JSTC], 2, [1, 1, 1], 1>;
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defm : X86WriteRes<WriteFStoreX, [JSAGU, JFPU1, JSTC], 1, [1, 1, 1], 1>;
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defm : X86WriteRes<WriteFStoreY, [JSAGU, JFPU1, JSTC], 1, [1, 1, 1], 1>;
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defm : X86WriteRes<WriteFStoreNT, [JSAGU, JFPU1, JSTC], 3, [1, 1, 1], 1>;
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defm : X86WriteRes<WriteFStoreNTX, [JSAGU, JFPU1, JSTC], 3, [1, 1, 1], 1>;
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defm : X86WriteRes<WriteFStoreNTY, [JSAGU, JFPU1, JSTC], 3, [2, 2, 2], 1>;
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defm : X86WriteRes<WriteFMaskedStore, [JSAGU, JFPU01, JFPX], 6, [1, 1, 4], 1>;
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defm : X86WriteRes<WriteFMaskedStoreY, [JSAGU, JFPU01, JFPX], 6, [2, 2, 4], 2>;
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defm : X86WriteRes<WriteFMove, [JFPU01, JFPX], 1, [1, 1], 1>;
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defm : X86WriteRes<WriteFMoveX, [JFPU01, JFPX], 1, [1, 1], 1>;
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defm : X86WriteRes<WriteFMoveY, [JFPU01, JFPX], 1, [2, 2], 2>;
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defm : X86WriteRes<WriteEMMS, [JFPU01, JFPX], 2, [1, 1], 1>;
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defm : JWriteResFpuPair<WriteFAdd, [JFPU0, JFPA], 3>;
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defm : JWriteResFpuPair<WriteFAddX, [JFPU0, JFPA], 3>;
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defm : JWriteResYMMPair<WriteFAddY, [JFPU0, JFPA], 3, [2,2], 2>;
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defm : X86WriteResPairUnsupported<WriteFAddZ>;
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defm : JWriteResFpuPair<WriteFAdd64, [JFPU0, JFPA], 3>;
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defm : JWriteResFpuPair<WriteFAdd64X, [JFPU0, JFPA], 3>;
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defm : JWriteResYMMPair<WriteFAdd64Y, [JFPU0, JFPA], 3, [2,2], 2>;
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defm : X86WriteResPairUnsupported<WriteFAdd64Z>;
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defm : JWriteResFpuPair<WriteFCmp, [JFPU0, JFPA], 2>;
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defm : JWriteResFpuPair<WriteFCmpX, [JFPU0, JFPA], 2>;
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defm : JWriteResYMMPair<WriteFCmpY, [JFPU0, JFPA], 2, [2,2], 2>;
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defm : X86WriteResPairUnsupported<WriteFCmpZ>;
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defm : JWriteResFpuPair<WriteFCmp64, [JFPU0, JFPA], 2>;
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defm : JWriteResFpuPair<WriteFCmp64X, [JFPU0, JFPA], 2>;
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defm : JWriteResYMMPair<WriteFCmp64Y, [JFPU0, JFPA], 2, [2,2], 2>;
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defm : X86WriteResPairUnsupported<WriteFCmp64Z>;
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defm : JWriteResFpuPair<WriteFCom, [JFPU0, JFPA, JALU0], 3>;
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defm : JWriteResFpuPair<WriteFMul, [JFPU1, JFPM], 2>;
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defm : JWriteResFpuPair<WriteFMulX, [JFPU1, JFPM], 2>;
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defm : JWriteResYMMPair<WriteFMulY, [JFPU1, JFPM], 2, [2,2], 2>;
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defm : X86WriteResPairUnsupported<WriteFMulZ>;
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defm : JWriteResFpuPair<WriteFMul64, [JFPU1, JFPM], 4, [1,2]>;
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defm : JWriteResFpuPair<WriteFMul64X, [JFPU1, JFPM], 4, [1,2]>;
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defm : JWriteResYMMPair<WriteFMul64Y, [JFPU1, JFPM], 4, [2,4], 2>;
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defm : X86WriteResPairUnsupported<WriteFMul64Z>;
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defm : X86WriteResPairUnsupported<WriteFMA>;
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defm : X86WriteResPairUnsupported<WriteFMAX>;
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defm : X86WriteResPairUnsupported<WriteFMAY>;
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defm : X86WriteResPairUnsupported<WriteFMAZ>;
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defm : JWriteResFpuPair<WriteDPPD, [JFPU1, JFPM, JFPA], 9, [1, 3, 3], 3>;
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defm : JWriteResFpuPair<WriteDPPS, [JFPU1, JFPM, JFPA], 11, [1, 3, 3], 5>;
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defm : JWriteResYMMPair<WriteDPPSY, [JFPU1, JFPM, JFPA], 12, [2, 6, 6], 10>;
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defm : X86WriteResPairUnsupported<WriteDPPSZ>;
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defm : JWriteResFpuPair<WriteFRcp, [JFPU1, JFPM], 2>;
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defm : JWriteResFpuPair<WriteFRcpX, [JFPU1, JFPM], 2>;
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defm : JWriteResYMMPair<WriteFRcpY, [JFPU1, JFPM], 2, [2,2], 2>;
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defm : X86WriteResPairUnsupported<WriteFRcpZ>;
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defm : JWriteResFpuPair<WriteFRsqrt, [JFPU1, JFPM], 2>;
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defm : JWriteResFpuPair<WriteFRsqrtX, [JFPU1, JFPM], 2>;
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defm : JWriteResYMMPair<WriteFRsqrtY, [JFPU1, JFPM], 2, [2,2], 2>;
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defm : X86WriteResPairUnsupported<WriteFRsqrtZ>;
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defm : JWriteResFpuPair<WriteFDiv, [JFPU1, JFPM], 19, [1, 19]>;
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defm : JWriteResFpuPair<WriteFDivX, [JFPU1, JFPM], 19, [1, 19]>;
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defm : JWriteResYMMPair<WriteFDivY, [JFPU1, JFPM], 38, [2, 38], 2>;
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defm : X86WriteResPairUnsupported<WriteFDivZ>;
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defm : JWriteResFpuPair<WriteFDiv64, [JFPU1, JFPM], 19, [1, 19]>;
|
|
defm : JWriteResFpuPair<WriteFDiv64X, [JFPU1, JFPM], 19, [1, 19]>;
|
|
defm : JWriteResYMMPair<WriteFDiv64Y, [JFPU1, JFPM], 38, [2, 38], 2>;
|
|
defm : X86WriteResPairUnsupported<WriteFDiv64Z>;
|
|
defm : JWriteResFpuPair<WriteFSqrt, [JFPU1, JFPM], 21, [1, 21]>;
|
|
defm : JWriteResFpuPair<WriteFSqrtX, [JFPU1, JFPM], 21, [1, 21]>;
|
|
defm : JWriteResYMMPair<WriteFSqrtY, [JFPU1, JFPM], 42, [2, 42], 2>;
|
|
defm : X86WriteResPairUnsupported<WriteFSqrtZ>;
|
|
defm : JWriteResFpuPair<WriteFSqrt64, [JFPU1, JFPM], 27, [1, 27]>;
|
|
defm : JWriteResFpuPair<WriteFSqrt64X, [JFPU1, JFPM], 27, [1, 27]>;
|
|
defm : JWriteResYMMPair<WriteFSqrt64Y, [JFPU1, JFPM], 54, [2, 54], 2>;
|
|
defm : X86WriteResPairUnsupported<WriteFSqrt64Z>;
|
|
defm : JWriteResFpuPair<WriteFSqrt80, [JFPU1, JFPM], 35, [1, 35]>;
|
|
defm : JWriteResFpuPair<WriteFSign, [JFPU1, JFPM], 2>;
|
|
defm : JWriteResFpuPair<WriteFRnd, [JFPU1, JSTC], 3>;
|
|
defm : JWriteResYMMPair<WriteFRndY, [JFPU1, JSTC], 3, [2,2], 2>;
|
|
defm : X86WriteResPairUnsupported<WriteFRndZ>;
|
|
defm : JWriteResFpuPair<WriteFLogic, [JFPU01, JFPX], 1>;
|
|
defm : JWriteResYMMPair<WriteFLogicY, [JFPU01, JFPX], 1, [2, 2], 2>;
|
|
defm : X86WriteResPairUnsupported<WriteFLogicZ>;
|
|
defm : JWriteResFpuPair<WriteFTest, [JFPU0, JFPA, JALU0], 3>;
|
|
defm : JWriteResYMMPair<WriteFTestY , [JFPU01, JFPX, JFPA, JALU0], 4, [2, 2, 2, 1], 3>;
|
|
defm : X86WriteResPairUnsupported<WriteFTestZ>;
|
|
defm : JWriteResFpuPair<WriteFShuffle, [JFPU01, JFPX], 1>;
|
|
defm : JWriteResYMMPair<WriteFShuffleY, [JFPU01, JFPX], 1, [2, 2], 2>;
|
|
defm : X86WriteResPairUnsupported<WriteFShuffleZ>;
|
|
defm : JWriteResFpuPair<WriteFVarShuffle, [JFPU01, JFPX], 2, [1, 4], 3>;
|
|
defm : JWriteResYMMPair<WriteFVarShuffleY,[JFPU01, JFPX], 3, [2, 6], 6>;
|
|
defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>;
|
|
defm : JWriteResFpuPair<WriteFBlend, [JFPU01, JFPX], 1>;
|
|
defm : JWriteResYMMPair<WriteFBlendY, [JFPU01, JFPX], 1, [2, 2], 2>;
|
|
defm : X86WriteResPairUnsupported<WriteFBlendZ>;
|
|
defm : JWriteResFpuPair<WriteFVarBlend, [JFPU01, JFPX], 2, [1, 4], 3>;
|
|
defm : JWriteResYMMPair<WriteFVarBlendY, [JFPU01, JFPX], 3, [2, 6], 6>;
|
|
defm : X86WriteResPairUnsupported<WriteFVarBlendZ>;
|
|
defm : JWriteResFpuPair<WriteFShuffle256, [JFPU01, JFPX], 1>;
|
|
defm : X86WriteResPairUnsupported<WriteFVarShuffle256>;
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
// Conversions.
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
|
|
defm : JWriteResFpuPair<WriteCvtSS2I, [JFPU1, JSTC, JFPA, JALU0], 7, [1,1,1,1], 2>;
|
|
defm : JWriteResFpuPair<WriteCvtPS2I, [JFPU1, JSTC], 3, [1,1], 1>;
|
|
defm : JWriteResYMMPair<WriteCvtPS2IY, [JFPU1, JSTC], 3, [2,2], 2>;
|
|
defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>;
|
|
defm : JWriteResFpuPair<WriteCvtSD2I, [JFPU1, JSTC, JFPA, JALU0], 7, [1,1,1,1], 2>;
|
|
defm : JWriteResFpuPair<WriteCvtPD2I, [JFPU1, JSTC], 3, [1,1], 1>;
|
|
defm : JWriteResYMMPair<WriteCvtPD2IY, [JFPU1, JSTC, JFPX], 6, [2,2,4], 3>;
|
|
defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>;
|
|
|
|
// FIXME: f+3 ST, LD+STC latency
|
|
defm : JWriteResFpuPair<WriteCvtI2SS, [JFPU1, JSTC], 9, [1,1], 2>;
|
|
defm : JWriteResFpuPair<WriteCvtI2PS, [JFPU1, JSTC], 3, [1,1], 1>;
|
|
defm : JWriteResYMMPair<WriteCvtI2PSY, [JFPU1, JSTC], 3, [2,2], 2>;
|
|
defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>;
|
|
defm : JWriteResFpuPair<WriteCvtI2SD, [JFPU1, JSTC], 9, [1,1], 2>;
|
|
defm : JWriteResFpuPair<WriteCvtI2PD, [JFPU1, JSTC], 3, [1,1], 1>;
|
|
defm : JWriteResYMMPair<WriteCvtI2PDY, [JFPU1, JSTC], 3, [2,2], 2>;
|
|
defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>;
|
|
|
|
defm : JWriteResFpuPair<WriteCvtSS2SD, [JFPU1, JSTC], 7, [1,2], 2>;
|
|
defm : JWriteResFpuPair<WriteCvtPS2PD, [JFPU1, JSTC], 2, [1,1], 1>;
|
|
defm : JWriteResYMMPair<WriteCvtPS2PDY, [JFPU1, JSTC], 2, [2,2], 2>;
|
|
defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>;
|
|
|
|
defm : JWriteResFpuPair<WriteCvtSD2SS, [JFPU1, JSTC], 7, [1,2], 2>;
|
|
defm : JWriteResFpuPair<WriteCvtPD2PS, [JFPU1, JSTC], 3, [1,1], 1>;
|
|
defm : JWriteResYMMPair<WriteCvtPD2PSY, [JFPU1, JSTC, JFPX], 6, [2,2,4], 3>;
|
|
defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>;
|
|
|
|
defm : JWriteResFpuPair<WriteCvtPH2PS, [JFPU1, JSTC], 3, [1,1], 1>;
|
|
defm : JWriteResYMMPair<WriteCvtPH2PSY, [JFPU1, JSTC], 3, [2,2], 2>;
|
|
defm : X86WriteResPairUnsupported<WriteCvtPH2PSZ>;
|
|
|
|
defm : X86WriteRes<WriteCvtPS2PH, [JFPU1, JSTC], 3, [1,1], 1>;
|
|
defm : X86WriteRes<WriteCvtPS2PHY, [JFPU1, JSTC, JFPX], 6, [2,2,2], 3>;
|
|
defm : X86WriteResUnsupported<WriteCvtPS2PHZ>;
|
|
defm : X86WriteRes<WriteCvtPS2PHSt, [JFPU1, JSTC, JSAGU], 4, [1,1,1], 1>;
|
|
defm : X86WriteRes<WriteCvtPS2PHYSt, [JFPU1, JSTC, JFPX, JSAGU], 7, [2,2,2,1], 3>;
|
|
defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>;
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
// Vector integer operations.
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
|
|
defm : X86WriteRes<WriteVecLoad, [JLAGU, JFPU01, JVALU], 5, [1, 1, 1], 1>;
|
|
defm : X86WriteRes<WriteVecLoadX, [JLAGU, JFPU01, JVALU], 5, [1, 1, 1], 1>;
|
|
defm : X86WriteRes<WriteVecLoadY, [JLAGU, JFPU01, JVALU], 5, [1, 1, 1], 1>;
|
|
defm : X86WriteRes<WriteVecLoadNT, [JLAGU, JFPU01, JVALU], 5, [1, 1, 1], 1>;
|
|
defm : X86WriteRes<WriteVecLoadNTY, [JLAGU, JFPU01, JVALU], 5, [1, 1, 1], 1>;
|
|
defm : X86WriteRes<WriteVecMaskedLoad, [JLAGU, JFPU01, JVALU], 6, [1, 1, 2], 1>;
|
|
defm : X86WriteRes<WriteVecMaskedLoadY, [JLAGU, JFPU01, JVALU], 6, [2, 2, 4], 2>;
|
|
|
|
defm : X86WriteRes<WriteVecStore, [JSAGU, JFPU1, JSTC], 2, [1, 1, 1], 1>;
|
|
defm : X86WriteRes<WriteVecStoreX, [JSAGU, JFPU1, JSTC], 1, [1, 1, 1], 1>;
|
|
defm : X86WriteRes<WriteVecStoreY, [JSAGU, JFPU1, JSTC], 1, [1, 1, 1], 1>;
|
|
defm : X86WriteRes<WriteVecStoreNT, [JSAGU, JFPU1, JSTC], 2, [1, 1, 1], 1>;
|
|
defm : X86WriteRes<WriteVecStoreNTY, [JSAGU, JFPU1, JSTC], 2, [2, 2, 2], 1>;
|
|
defm : X86WriteRes<WriteVecMaskedStore, [JSAGU, JFPU01, JVALU], 6, [1, 1, 4], 1>;
|
|
defm : X86WriteRes<WriteVecMaskedStoreY, [JSAGU, JFPU01, JVALU], 6, [2, 2, 4], 2>;
|
|
|
|
defm : X86WriteRes<WriteVecMove, [JFPU01, JVALU], 1, [1, 1], 1>;
|
|
defm : X86WriteRes<WriteVecMoveX, [JFPU01, JVALU], 1, [1, 1], 1>;
|
|
defm : X86WriteRes<WriteVecMoveY, [JFPU01, JVALU], 1, [2, 2], 2>;
|
|
defm : X86WriteRes<WriteVecMoveToGpr, [JFPU0, JFPA, JALU0], 4, [1, 1, 1], 1>;
|
|
defm : X86WriteRes<WriteVecMoveFromGpr, [JFPU01, JFPX], 8, [1, 1], 2>;
|
|
|
|
defm : JWriteResFpuPair<WriteVecALU, [JFPU01, JVALU], 1>;
|
|
defm : JWriteResFpuPair<WriteVecALUX, [JFPU01, JVALU], 1>;
|
|
defm : X86WriteResPairUnsupported<WriteVecALUY>;
|
|
defm : X86WriteResPairUnsupported<WriteVecALUZ>;
|
|
defm : JWriteResFpuPair<WriteVecShift, [JFPU01, JVALU], 1>;
|
|
defm : JWriteResFpuPair<WriteVecShiftX, [JFPU01, JVALU], 1>;
|
|
defm : X86WriteResPairUnsupported<WriteVecShiftY>;
|
|
defm : X86WriteResPairUnsupported<WriteVecShiftZ>;
|
|
defm : JWriteResFpuPair<WriteVecShiftImm, [JFPU01, JVALU], 1>;
|
|
defm : JWriteResFpuPair<WriteVecShiftImmX,[JFPU01, JVALU], 1>;
|
|
defm : X86WriteResPairUnsupported<WriteVecShiftImmY>;
|
|
defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>;
|
|
defm : X86WriteResPairUnsupported<WriteVarVecShift>;
|
|
defm : X86WriteResPairUnsupported<WriteVarVecShiftY>;
|
|
defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>;
|
|
defm : JWriteResFpuPair<WriteVecIMul, [JFPU0, JVIMUL], 2>;
|
|
defm : JWriteResFpuPair<WriteVecIMulX, [JFPU0, JVIMUL], 2>;
|
|
defm : X86WriteResPairUnsupported<WriteVecIMulY>;
|
|
defm : X86WriteResPairUnsupported<WriteVecIMulZ>;
|
|
defm : JWriteResFpuPair<WritePMULLD, [JFPU0, JFPU01, JVIMUL, JVALU], 4, [2, 1, 2, 1], 3>;
|
|
defm : X86WriteResPairUnsupported<WritePMULLDY>;
|
|
defm : X86WriteResPairUnsupported<WritePMULLDZ>;
|
|
defm : JWriteResFpuPair<WriteMPSAD, [JFPU0, JVIMUL], 3, [1, 2]>;
|
|
defm : X86WriteResPairUnsupported<WriteMPSADY>;
|
|
defm : X86WriteResPairUnsupported<WriteMPSADZ>;
|
|
defm : JWriteResFpuPair<WritePSADBW, [JFPU01, JVALU], 2>;
|
|
defm : JWriteResFpuPair<WritePSADBWX, [JFPU01, JVALU], 2>;
|
|
defm : X86WriteResPairUnsupported<WritePSADBWY>;
|
|
defm : X86WriteResPairUnsupported<WritePSADBWZ>;
|
|
defm : JWriteResFpuPair<WritePHMINPOS, [JFPU0, JVALU], 2>;
|
|
defm : JWriteResFpuPair<WriteShuffle, [JFPU01, JVALU], 1>;
|
|
defm : JWriteResFpuPair<WriteShuffleX, [JFPU01, JVALU], 1>;
|
|
defm : X86WriteResPairUnsupported<WriteShuffleY>;
|
|
defm : X86WriteResPairUnsupported<WriteShuffleZ>;
|
|
defm : JWriteResFpuPair<WriteVarShuffle, [JFPU01, JVALU], 2, [1, 4], 3>;
|
|
defm : JWriteResFpuPair<WriteVarShuffleX, [JFPU01, JVALU], 2, [1, 4], 3>;
|
|
defm : X86WriteResPairUnsupported<WriteVarShuffleY>;
|
|
defm : X86WriteResPairUnsupported<WriteVarShuffleZ>;
|
|
defm : JWriteResFpuPair<WriteBlend, [JFPU01, JVALU], 1>;
|
|
defm : X86WriteResPairUnsupported<WriteBlendY>;
|
|
defm : X86WriteResPairUnsupported<WriteBlendZ>;
|
|
defm : JWriteResFpuPair<WriteVarBlend, [JFPU01, JVALU], 2, [1, 4], 3>;
|
|
defm : X86WriteResPairUnsupported<WriteVarBlendY>;
|
|
defm : X86WriteResPairUnsupported<WriteVarBlendZ>;
|
|
defm : JWriteResFpuPair<WriteVecLogic, [JFPU01, JVALU], 1>;
|
|
defm : JWriteResFpuPair<WriteVecLogicX, [JFPU01, JVALU], 1>;
|
|
defm : X86WriteResPairUnsupported<WriteVecLogicY>;
|
|
defm : X86WriteResPairUnsupported<WriteVecLogicZ>;
|
|
defm : JWriteResFpuPair<WriteVecTest, [JFPU0, JFPA, JALU0], 3>;
|
|
defm : JWriteResYMMPair<WriteVecTestY, [JFPU01, JFPX, JFPA, JALU0], 4, [2, 2, 2, 1], 3>;
|
|
defm : X86WriteResPairUnsupported<WriteVecTestZ>;
|
|
defm : X86WriteResPairUnsupported<WriteShuffle256>;
|
|
defm : X86WriteResPairUnsupported<WriteVarShuffle256>;
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
// Vector insert/extract operations.
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
|
|
defm : X86WriteRes<WriteVecInsert, [JFPU01, JVALU], 7, [1,1], 2>;
|
|
defm : X86WriteRes<WriteVecInsertLd, [JFPU01, JVALU, JLAGU], 4, [1,1,1], 1>;
|
|
defm : X86WriteRes<WriteVecExtract, [JFPU0, JFPA, JALU0], 3, [1,1,1], 1>;
|
|
defm : X86WriteRes<WriteVecExtractSt, [JFPU1, JSTC, JSAGU], 3, [1,1,1], 1>;
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
// SSE42 String instructions.
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
|
|
defm : JWriteResFpuPair<WritePCmpIStrI, [JFPU1, JVALU1, JFPA, JALU0], 7, [1, 2, 1, 1], 3>;
|
|
defm : JWriteResFpuPair<WritePCmpIStrM, [JFPU1, JVALU1, JFPA, JALU0], 8, [1, 2, 1, 1], 3>;
|
|
defm : JWriteResFpuPair<WritePCmpEStrI, [JFPU1, JSAGU, JLAGU, JVALU, JVALU1, JFPA, JALU0], 14, [1, 2, 2, 6, 4, 1, 1], 9>;
|
|
defm : JWriteResFpuPair<WritePCmpEStrM, [JFPU1, JSAGU, JLAGU, JVALU, JVALU1, JFPA, JALU0], 14, [1, 2, 2, 6, 4, 1, 1], 9>;
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
// MOVMSK Instructions.
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
|
|
def : WriteRes<WriteFMOVMSK, [JFPU0, JFPA, JALU0]> { let Latency = 3; }
|
|
def : WriteRes<WriteVecMOVMSK, [JFPU0, JFPA, JALU0]> { let Latency = 3; }
|
|
defm : X86WriteResUnsupported<WriteVecMOVMSKY>;
|
|
def : WriteRes<WriteMMXMOVMSK, [JFPU0, JFPA, JALU0]> { let Latency = 3; }
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
// AES Instructions.
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
|
|
defm : JWriteResFpuPair<WriteAESIMC, [JFPU0, JVIMUL], 2>;
|
|
defm : JWriteResFpuPair<WriteAESKeyGen, [JFPU0, JVIMUL], 2>;
|
|
defm : JWriteResFpuPair<WriteAESDecEnc, [JFPU0, JVIMUL], 3, [1, 1], 2>;
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
// Horizontal add/sub instructions.
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
|
|
defm : JWriteResFpuPair<WriteFHAdd, [JFPU0, JFPA], 3>;
|
|
defm : JWriteResYMMPair<WriteFHAddY, [JFPU0, JFPA], 3, [2,2], 2>;
|
|
defm : JWriteResFpuPair<WritePHAdd, [JFPU01, JVALU], 1>;
|
|
defm : JWriteResFpuPair<WritePHAddX, [JFPU01, JVALU], 1>;
|
|
defm : X86WriteResPairUnsupported<WritePHAddY>;
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
// Carry-less multiplication instructions.
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
|
|
defm : JWriteResFpuPair<WriteCLMul, [JFPU0, JVIMUL], 2>;
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
// SSE4A instructions.
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
|
|
def JWriteINSERTQ: SchedWriteRes<[JFPU01, JVALU]> {
|
|
let Latency = 2;
|
|
let ResourceCycles = [1, 4];
|
|
}
|
|
def : InstRW<[JWriteINSERTQ], (instrs INSERTQ, INSERTQI)>;
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
// AVX instructions.
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
|
|
def JWriteVBROADCASTYLd: SchedWriteRes<[JLAGU, JFPU01, JFPX]> {
|
|
let Latency = 6;
|
|
let ResourceCycles = [1, 2, 4];
|
|
let NumMicroOps = 2;
|
|
}
|
|
def : InstRW<[JWriteVBROADCASTYLd, ReadAfterLd], (instrs VBROADCASTSDYrm,
|
|
VBROADCASTSSYrm)>;
|
|
|
|
def JWriteJVZEROALL: SchedWriteRes<[]> {
|
|
let Latency = 90;
|
|
let NumMicroOps = 73;
|
|
}
|
|
def : InstRW<[JWriteJVZEROALL], (instrs VZEROALL)>;
|
|
|
|
def JWriteJVZEROUPPER: SchedWriteRes<[]> {
|
|
let Latency = 46;
|
|
let NumMicroOps = 37;
|
|
}
|
|
def : InstRW<[JWriteJVZEROUPPER], (instrs VZEROUPPER)>;
|
|
|
|
///////////////////////////////////////////////////////////////////////////////
|
|
// SchedWriteVariant definitions.
|
|
///////////////////////////////////////////////////////////////////////////////
|
|
|
|
def JWriteZeroLatency : SchedWriteRes<[]> {
|
|
let Latency = 0;
|
|
}
|
|
|
|
// Certain instructions that use the same register for both source
|
|
// operands do not have a real dependency on the previous contents of the
|
|
// register, and thus, do not have to wait before completing. They can be
|
|
// optimized out at register renaming stage.
|
|
// Reference: Section 10.8 of the "Software Optimization Guide for AMD Family
|
|
// 15h Processors".
|
|
// Reference: Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs",
|
|
// Section 21.8 [Dependency-breaking instructions].
|
|
|
|
def JWriteZeroIdiom : SchedWriteVariant<[
|
|
SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [JWriteZeroLatency]>,
|
|
SchedVar<MCSchedPredicate<TruePred>, [WriteALU]>
|
|
]>;
|
|
def : InstRW<[JWriteZeroIdiom], (instrs SUB32rr, SUB64rr,
|
|
XOR32rr, XOR64rr)>;
|
|
|
|
def JWriteFZeroIdiom : SchedWriteVariant<[
|
|
SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [JWriteZeroLatency]>,
|
|
SchedVar<MCSchedPredicate<TruePred>, [WriteFLogic]>
|
|
]>;
|
|
def : InstRW<[JWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr, XORPDrr, VXORPDrr,
|
|
ANDNPSrr, VANDNPSrr,
|
|
ANDNPDrr, VANDNPDrr)>;
|
|
|
|
def JWriteVZeroIdiomLogic : SchedWriteVariant<[
|
|
SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [JWriteZeroLatency]>,
|
|
SchedVar<MCSchedPredicate<TruePred>, [WriteVecLogic]>
|
|
]>;
|
|
def : InstRW<[JWriteVZeroIdiomLogic], (instrs MMX_PXORirr, MMX_PANDNirr)>;
|
|
|
|
def JWriteVZeroIdiomLogicX : SchedWriteVariant<[
|
|
SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [JWriteZeroLatency]>,
|
|
SchedVar<MCSchedPredicate<TruePred>, [WriteVecLogicX]>
|
|
]>;
|
|
def : InstRW<[JWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr,
|
|
PANDNrr, VPANDNrr)>;
|
|
|
|
def JWriteVZeroIdiomALU : SchedWriteVariant<[
|
|
SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [JWriteZeroLatency]>,
|
|
SchedVar<MCSchedPredicate<TruePred>, [WriteVecALU]>
|
|
]>;
|
|
def : InstRW<[JWriteVZeroIdiomALU], (instrs MMX_PSUBBirr, MMX_PSUBDirr,
|
|
MMX_PSUBQirr, MMX_PSUBWirr,
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MMX_PCMPGTBirr, MMX_PCMPGTDirr,
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MMX_PCMPGTWirr)>;
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def JWriteVZeroIdiomALUX : SchedWriteVariant<[
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SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [JWriteZeroLatency]>,
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SchedVar<MCSchedPredicate<TruePred>, [WriteVecALUX]>
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]>;
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def : InstRW<[JWriteVZeroIdiomALUX], (instrs PSUBBrr, VPSUBBrr,
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PSUBDrr, VPSUBDrr,
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PSUBQrr, VPSUBQrr,
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PSUBWrr, VPSUBWrr,
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PCMPGTBrr, VPCMPGTBrr,
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PCMPGTDrr, VPCMPGTDrr,
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PCMPGTQrr, VPCMPGTQrr,
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PCMPGTWrr, VPCMPGTWrr)>;
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} // SchedModel
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