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334 lines
13 KiB
C++
334 lines
13 KiB
C++
//===- IA64InstrInfo.td - Describe the IA64 Instruction Set -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Duraid Madina and is distributed under the
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// University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the IA64 instruction set, defining the instructions, and
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// properties of the instructions which are needed for code generation, machine
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// code emission, and analysis.
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//
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//===----------------------------------------------------------------------===//
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include "IA64InstrFormats.td"
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def u6imm : Operand<i8>;
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def s16imm : Operand<i16>;
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def s21imm : Operand<i32> {
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let PrintMethod = "printS21ImmOperand";
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}
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def u32imm : Operand<i32> {
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let PrintMethod = "printU32ImmOperand";
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}
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def s32imm : Operand<i32> {
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let PrintMethod = "printS32ImmOperand";
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}
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def u64imm : Operand<i64> {
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let PrintMethod = "printU64ImmOperand";
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}
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// the asmprinter needs to know about calls
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let PrintMethod = "printCallOperand" in
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def calltarget : Operand<i64>;
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def PHI : PseudoInstIA64<(ops), "PHI">;
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def IDEF : PseudoInstIA64<(ops), "// IDEF">;
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def WTF : PseudoInstIA64<(ops), "que??">;
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def ADJUSTCALLSTACKUP : PseudoInstIA64<(ops), "// ADJUSTCALLSTACKUP">;
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def ADJUSTCALLSTACKDOWN : PseudoInstIA64<(ops), "// ADJUSTCALLSTACKDOWN">;
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def PSEUDO_ALLOC : PseudoInstIA64<(ops), "// PSEUDO_ALLOC">;
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def ALLOC : AForm<0x03, 0x0b,
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(ops GR:$dst, i8imm:$inputs, i8imm:$locals, i8imm:$outputs, i8imm:$rotating),
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"alloc $dst = ar.pfs,$inputs,$locals,$outputs,$rotating;;">;
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def MOV : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src), "mov $dst = $src;;">;
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def PMOV : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src, PR:$qp),
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"($qp) mov $dst = $src;;">;
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def SPILL_ALL_PREDICATES_TO_GR : AForm<0x03, 0x0b, (ops GR:$dst),
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"mov $dst = pr;;">;
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def FILL_ALL_PREDICATES_FROM_GR : AForm<0x03, 0x0b, (ops GR:$src),
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"mov pr = $src;;">;
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let isTwoAddress = 1 in {
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def CMOV : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src2, GR:$src, PR:$qp),
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"($qp) mov $dst = $src;;">;
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}
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def PFMOV : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src, PR:$qp),
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"($qp) mov $dst = $src;;">;
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let isTwoAddress = 1 in {
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def CFMOV : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src2, FP:$src, PR:$qp),
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"($qp) mov $dst = $src;;">;
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}
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let isTwoAddress = 1 in {
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def TCMPNE : AForm<0x03, 0x0b,
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(ops PR:$dst, PR:$src2, GR:$src3, GR:$src4),
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"cmp.ne $dst, p0 = $src3, $src4;;">;
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def TPCMPEQOR : AForm<0x03, 0x0b,
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(ops PR:$dst, PR:$src2, GR:$src3, GR:$src4, PR:$qp),
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"($qp) cmp.eq.or $dst, p0 = $src3, $src4;;">;
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def TPCMPNE : AForm<0x03, 0x0b,
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(ops PR:$dst, PR:$src2, GR:$src3, GR:$src4, PR:$qp),
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"($qp) cmp.ne $dst, p0 = $src3, $src4;;">;
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def TPCMPEQ : AForm<0x03, 0x0b,
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(ops PR:$dst, PR:$src2, GR:$src3, GR:$src4, PR:$qp),
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"($qp) cmp.eq $dst, p0 = $src3, $src4;;">;
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}
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def MOVI32 : AForm<0x03, 0x0b, (ops GR:$dst, u32imm:$imm),
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"mov $dst = $imm;;">;
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def MOVLI32 : AForm<0x03, 0x0b, (ops GR:$dst, u32imm:$imm),
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"movl $dst = $imm;;">;
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def MOVLSI32 : AForm<0x03, 0x0b, (ops GR:$dst, s32imm:$imm),
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"movl $dst = $imm;;">;
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def MOVLI64 : AForm<0x03, 0x0b, (ops GR:$dst, u64imm:$imm),
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"movl $dst = $imm;;">;
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def AND : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
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"and $dst = $src1, $src2;;">;
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def OR : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
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"or $dst = $src1, $src2;;">;
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def XOR : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
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"xor $dst = $src1, $src2;;">;
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def SHL : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
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"shl $dst = $src1, $src2;;">;
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def SHLI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s21imm:$imm),
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"shl $dst = $src1, $imm;;">; // FIXME: 6 immediate bits, not 21
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def SHRU : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
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"shr.u $dst = $src1, $src2;;">;
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def SHRS : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
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"shr $dst = $src1, $src2;;">;
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def DEPZ : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm1, u6imm:$imm2), "dep.z $dst = $src1, $imm1, $imm2;;">;
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def SXT1 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src), "sxt1 $dst = $src;;">;
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def ZXT1 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src), "zxt1 $dst = $src;;">;
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def SXT2 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src), "sxt2 $dst = $src;;">;
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def ZXT2 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src), "zxt2 $dst = $src;;">;
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def SXT4 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src), "sxt4 $dst = $src;;">;
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def ZXT4 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src), "zxt4 $dst = $src;;">;
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// the following are all a bit unfortunate: we throw away the complement
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// of the compare!
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def CMPEQ : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
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"cmp.eq $dst, p0 = $src1, $src2;;">;
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def CMPGT : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
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"cmp.gt $dst, p0 = $src1, $src2;;">;
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def CMPGE : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
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"cmp.ge $dst, p0 = $src1, $src2;;">;
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def CMPLT : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
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"cmp.lt $dst, p0 = $src1, $src2;;">;
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def CMPLE : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
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"cmp.le $dst, p0 = $src1, $src2;;">;
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def CMPNE : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
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"cmp.ne $dst, p0 = $src1, $src2;;">;
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def CMPLTU : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
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"cmp.ltu $dst, p0 = $src1, $src2;;">;
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def CMPGTU : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
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"cmp.gtu $dst, p0 = $src1, $src2;;">;
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def CMPLEU : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
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"cmp.leu $dst, p0 = $src1, $src2;;">;
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def CMPGEU : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
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"cmp.geu $dst, p0 = $src1, $src2;;">;
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// and we do the whole thing again for FP compares!
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def FCMPEQ : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
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"fcmp.eq $dst, p0 = $src1, $src2;;">;
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def FCMPGT : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
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"fcmp.gt $dst, p0 = $src1, $src2;;">;
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def FCMPGE : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
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"fcmp.ge $dst, p0 = $src1, $src2;;">;
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def FCMPLT : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
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"fcmp.lt $dst, p0 = $src1, $src2;;">;
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def FCMPLE : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
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"fcmp.le $dst, p0 = $src1, $src2;;">;
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def FCMPNE : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
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"fcmp.neq $dst, p0 = $src1, $src2;;">;
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def FCMPLTU : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
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"fcmp.ltu $dst, p0 = $src1, $src2;;">;
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def FCMPGTU : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
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"fcmp.gtu $dst, p0 = $src1, $src2;;">;
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def FCMPLEU : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
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"fcmp.leu $dst, p0 = $src1, $src2;;">;
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def FCMPGEU : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
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"fcmp.geu $dst, p0 = $src1, $src2;;">;
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def PCMPEQOR : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2, PR:$qp),
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"($qp) cmp.eq.or $dst, p0 = $src1, $src2;;">;
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def PCMPEQUNC : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2, PR:$qp),
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"($qp) cmp.eq.unc $dst, p0 = $src1, $src2;;">;
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def PCMPNE : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2, PR:$qp),
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"($qp) cmp.ne $dst, p0 = $src1, $src2;;">;
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// two destinations!
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def BCMPEQ : AForm<0x03, 0x0b, (ops PR:$dst1, PR:$dst2, GR:$src1, GR:$src2),
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"cmp.eq $dst1, dst2 = $src1, $src2;;">;
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def ADD : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
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"add $dst = $src1, $src2;;">;
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def ADDIMM22 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s21imm:$imm),
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"add $dst = $imm, $src1;;">;
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def CADDIMM22 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s21imm:$imm, PR:$qp),
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"($qp) add $dst = $imm, $src1;;">;
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let isTwoAddress = 1 in {
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def TPCADDIMM22 : AForm<0x03, 0x0b,
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(ops GR:$dst, GR:$src1, s21imm:$imm, PR:$qp),
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"($qp) add $dst = $imm, $dst;;">;
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def TPCMPIMM8NE : AForm<0x03, 0x0b,
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(ops PR:$dst, PR:$src1, s21imm:$imm, GR:$src2, PR:$qp),
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"($qp) cmp.ne $dst , p0 = $imm, $src2;;">;
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}
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def SUB : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
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"sub $dst = $src1, $src2;;">;
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def ST1 : AForm<0x03, 0x0b, (ops GR:$dstPtr, GR:$value),
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"st1 [$dstPtr] = $value;;">;
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def ST2 : AForm<0x03, 0x0b, (ops GR:$dstPtr, GR:$value),
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"st2 [$dstPtr] = $value;;">;
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def ST4 : AForm<0x03, 0x0b, (ops GR:$dstPtr, GR:$value),
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"st4 [$dstPtr] = $value;;">;
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def ST8 : AForm<0x03, 0x0b, (ops GR:$dstPtr, GR:$value),
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"st8 [$dstPtr] = $value;;">;
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def LD1 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$srcPtr),
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"ld1 $dst = [$srcPtr];;">;
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def LD2 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$srcPtr),
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"ld2 $dst = [$srcPtr];;">;
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def LD4 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$srcPtr),
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"ld4 $dst = [$srcPtr];;">;
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def LD8 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$srcPtr),
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"ld8 $dst = [$srcPtr];;">;
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// some FP stuff:
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def FADD : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2),
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"fadd $dst = $src1, $src2;;">;
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def FADDS: AForm<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2),
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"fadd.s $dst = $src1, $src2;;">;
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def FSUB : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2),
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"fsub $dst = $src1, $src2;;">;
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def FMPY : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2),
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"fmpy $dst = $src1, $src2;;">;
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def FMOV : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
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"mov $dst = $src;;">; // XXX: there _is_ no fmov
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def FMA : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
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"fma $dst = $src1, $src2, $src3;;">;
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def FNMA : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
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"fnma $dst = $src1, $src2, $src3;;">;
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def FABS : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
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"fabs $dst = $src;;">;
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def FNEG : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
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"fneg $dst = $src;;">;
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def FNEGABS : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
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"fnegabs $dst = $src;;">;
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def CFMAS1 : AForm<0x03, 0x0b,
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(ops FP:$dst, FP:$src1, FP:$src2, FP:$src3, PR:$qp),
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"($qp) fma.s1 $dst = $src1, $src2, $src3;;">;
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def CFNMAS1 : AForm<0x03, 0x0b,
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(ops FP:$dst, FP:$src1, FP:$src2, FP:$src3, PR:$qp),
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"($qp) fnma.s1 $dst = $src1, $src2, $src3;;">;
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// FIXME: we 'explode' FRCPA (which should write two registers) into two
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// operations that write one each. this is a waste, and is also destroying
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// f127. not cool.
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def FRCPAS1FLOAT : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2),
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"frcpa.s1 $dst , p0 = $src1, $src2;;">;
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// XXX: this _will_ break things: (f127)
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def FRCPAS1PREDICATE : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
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"frcpa.s1 f127 , $dst = $src1, $src2;; // XXX FIXME!!!!">;
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def XMAL : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
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"xma.l $dst = $src1, $src2, $src3;;">;
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def FCVTXF : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
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"fcvt.xf $dst = $src;;">;
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def FCVTXUF : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
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"fcvt.xuf $dst = $src;;">;
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def FCVTXUFS1 : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
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"fcvt.xuf.s1 $dst = $src;;">;
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def FCVTFX : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
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"fcvt.fx $dst = $src;;">;
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def FCVTFXU : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
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"fcvt.fxu $dst = $src;;">;
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def FCVTFXTRUNC : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
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"fcvt.fx.trunc $dst = $src;;">;
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def FCVTFXUTRUNC : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
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"fcvt.fxu.trunc $dst = $src;;">;
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def FCVTFXTRUNCS1 : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
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"fcvt.fx.trunc.s1 $dst = $src;;">;
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def FCVTFXUTRUNCS1 : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
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"fcvt.fxu.trunc.s1 $dst = $src;;">;
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def FNORMD : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
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"fnorm.d $dst = $src;;">;
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def GETFD : AForm<0x03, 0x0b, (ops GR:$dst, FP:$src),
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"getf.d $dst = $src;;">;
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def SETFD : AForm<0x03, 0x0b, (ops FP:$dst, GR:$src),
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"setf.d $dst = $src;;">;
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def GETFSIG : AForm<0x03, 0x0b, (ops GR:$dst, FP:$src),
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"getf.sig $dst = $src;;">;
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def SETFSIG : AForm<0x03, 0x0b, (ops FP:$dst, GR:$src),
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"setf.sig $dst = $src;;">;
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def LDF4 : AForm<0x03, 0x0b, (ops FP:$dst, GR:$srcPtr),
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"ldfs $dst = [$srcPtr];;">;
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def LDF8 : AForm<0x03, 0x0b, (ops FP:$dst, GR:$srcPtr),
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"ldfd $dst = [$srcPtr];;">;
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def STF4 : AForm<0x03, 0x0b, (ops GR:$dstPtr, FP:$value),
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"stfs [$dstPtr] = $value;;">;
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def STF8 : AForm<0x03, 0x0b, (ops GR:$dstPtr, FP:$value),
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"stfd [$dstPtr] = $value;;">;
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let isTerminator = 1, isBranch = 1 in {
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def BRLCOND_NOTCALL : RawForm<0x03, 0xb0, (ops PR:$qp, i64imm:$dst),
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"($qp) brl.cond.sptk $dst;;">;
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def BRCOND_NOTCALL : RawForm<0x03, 0xb0, (ops PR:$qp, GR:$dst),
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"($qp) br.cond.sptk $dst;;">;
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}
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let isCall = 1, isTerminator = 1, isBranch = 1,
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// all calls clobber non-callee-saved registers, and for now, they are these:
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Defs = [r2,r3,r8,r9,r10,r11,r14,r15,r16,r17,r18,r19,r20,r21,r22,r23,r24,
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r25,r26,r27,r28,r29,r30,r31,
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p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,
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F6,F7,F8,F9,F10,F11,F12,F13,F14,F15,
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F32,F33,F34,F35,F36,F37,F38,F39,F40,F41,F42,F43,F44,F45,F46,F47,F48,F49,
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F50,F51,F52,F53,F54,F55,F56,
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F57,F58,F59,F60,F61,F62,F63,F64,F65,F66,F67,F68,F69,F70,F71,F72,F73,F74,
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F75,F76,F77,F78,F79,F80,F81,
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F82,F83,F84,F85,F86,F87,F88,F89,F90,F91,F92,F93,F94,F95,F96,F97,F98,F99,
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F100,F101,F102,F103,F104,F105,
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F106,F107,F108,F109,F110,F111,F112,F113,F114,F115,F116,F117,F118,F119,
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F120,F121,F122,F123,F124,F125,F126,F127,
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out0,out1,out2,out3,out4,out5,out6,out7] in {
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def BRCALL : RawForm<0x03, 0xb0, (ops calltarget:$dst),
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"br.call.sptk rp = $dst;;">; // FIXME: teach llvm about branch regs?
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def BRLCOND_CALL : RawForm<0x03, 0xb0, (ops PR:$qp, i64imm:$dst),
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"($qp) brl.cond.call.sptk $dst;;">;
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def BRCOND_CALL : RawForm<0x03, 0xb0, (ops PR:$qp, GR:$dst),
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"($qp) br.cond.call.sptk $dst;;">;
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}
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let isTerminator = 1, isReturn = 1 in
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def RET : RawForm<0x03, 0xb0, (ops), "br.ret.sptk.many rp;;">; // return
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