Geoff Berry 5377924081 [AArch64] Generate csinv instruction more often ... Reviewers: t.p.northover, jmolloy Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D17546 llvm-svn: 261675		2016-02-23 19:34:13 +00:00
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AArch64	[AArch64] Generate csinv instruction more often	2016-02-23 19:34:13 +00:00
AMDGPU	AMDGPU: Add failing testcase for register coalescer	2016-02-22 23:45:42 +00:00
ARM	ARM: sink atomic release barrier as far as possible into cmpxchg.	2016-02-22 20:55:50 +00:00
BPF
CPP
Generic
Hexagon
Inputs
Mips
MIR	When printing MIR, output to errs() rather than outs().	2016-02-19 00:18:46 +00:00
MSP430
NVPTX	Don't tail-duplicate blocks that contain convergent instructions.	2016-02-22 17:50:52 +00:00
PowerPC	Fix for PR26690 take 2	2016-02-22 18:04:00 +00:00
SPARC
SystemZ	[SystemZ] Fix ABI for i128 argument and return types	2016-02-19 14:10:21 +00:00
Thumb
Thumb2
WebAssembly	[WebAssembly] Implement red zone for user stack	2016-02-23 18:13:07 +00:00
WinEH	[WinEH] Visit 'unwind to caller' catchswitches nested in catchswitches	2016-02-23 07:18:15 +00:00
X86	Remove a space after a trailing backslash.	2016-02-23 11:19:56 +00:00
XCore