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https://github.com/RPCS3/llvm-mirror.git
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099f4c5254
Allow a target to do something other than search for copies that will avoid cross register bank copies. Implement for SI by only rewriting the most basic copies, so it should look through anything like a subregister extract. I'm not entirely satisified with this because it seems like eliminating a reg_sequence that isn't fully used should work generically for all targets without them having to override something. However, it seems to be tricky to have a simple implementation of this without rewriting to invalid kinds of subregister copies on some targets. I'm not sure if there is currently a generic way to easily check if a subregister index would be valid for the current use. The current set of TargetRegisterInfo::get*Class functions don't quite behave like I would expect (e.g. getSubClassWithSubReg returns the maximal register class rather than the minimal), so I'm not sure how to make the generic test keep searching if SrcRC:SrcSubReg is a valid replacement for DefRC:DefSubReg. Making the default implementation to check for simple copies breaks a variety of ARM and x86 tests by producing illegal subregister uses. The ARM tests are not actually changed since it should still be using the same sharesSameRegisterFile implementation, this just relaxes them to not check for specific registers. llvm-svn: 248478
256 lines
12 KiB
LLVM
256 lines
12 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -check-prefix=CI %s
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@lds = addrspace(3) global [512 x float] undef, align 4
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@lds.v2 = addrspace(3) global [512 x <2 x float>] undef, align 4
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@lds.v3 = addrspace(3) global [512 x <3 x float>] undef, align 4
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@lds.v4 = addrspace(3) global [512 x <4 x float>] undef, align 4
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@lds.v8 = addrspace(3) global [512 x <8 x float>] undef, align 4
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@lds.v16 = addrspace(3) global [512 x <16 x float>] undef, align 4
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; CI-LABEL: {{^}}simple_read2_v2f32_superreg_align4:
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; CI: ds_read2_b32 [[RESULT:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset1:1{{$}}
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; CI: s_waitcnt lgkmcnt(0)
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; CI: buffer_store_dwordx2 [[RESULT]]
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; CI: s_endpgm
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define void @simple_read2_v2f32_superreg_align4(<2 x float> addrspace(1)* %out) #0 {
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%x.i = tail call i32 @llvm.r600.read.tidig.x() #1
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%arrayidx0 = getelementptr inbounds [512 x <2 x float>], [512 x <2 x float>] addrspace(3)* @lds.v2, i32 0, i32 %x.i
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%val0 = load <2 x float>, <2 x float> addrspace(3)* %arrayidx0, align 4
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%out.gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %out, i32 %x.i
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store <2 x float> %val0, <2 x float> addrspace(1)* %out.gep
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ret void
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}
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; CI-LABEL: {{^}}simple_read2_v2f32_superreg:
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; CI: ds_read_b64 [[RESULT:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}{{$}}
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; CI: s_waitcnt lgkmcnt(0)
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; CI: buffer_store_dwordx2 [[RESULT]]
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; CI: s_endpgm
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define void @simple_read2_v2f32_superreg(<2 x float> addrspace(1)* %out) #0 {
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%x.i = tail call i32 @llvm.r600.read.tidig.x() #1
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%arrayidx0 = getelementptr inbounds [512 x <2 x float>], [512 x <2 x float>] addrspace(3)* @lds.v2, i32 0, i32 %x.i
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%val0 = load <2 x float>, <2 x float> addrspace(3)* %arrayidx0
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%out.gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %out, i32 %x.i
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store <2 x float> %val0, <2 x float> addrspace(1)* %out.gep
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ret void
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}
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; CI-LABEL: {{^}}simple_read2_v4f32_superreg_align4:
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_X:[0-9]+]]:[[REG_Y:[0-9]+]]{{\]}}, v{{[0-9]+}} offset1:1{{$}}
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_Z:[0-9]+]]:[[REG_W:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:2 offset1:3{{$}}
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; CI-DAG: v_add_f32_e32 v[[ADD0:[0-9]+]], v[[REG_Z]], v[[REG_X]]
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; CI-DAG: v_add_f32_e32 v[[ADD1:[0-9]+]], v[[REG_W]], v[[REG_Y]]
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; CI: v_add_f32_e32 v[[ADD2:[0-9]+]], v[[ADD1]], v[[ADD0]]
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; CI: buffer_store_dword v[[ADD2]]
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; CI: s_endpgm
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define void @simple_read2_v4f32_superreg_align4(float addrspace(1)* %out) #0 {
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%x.i = tail call i32 @llvm.r600.read.tidig.x() #1
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%arrayidx0 = getelementptr inbounds [512 x <4 x float>], [512 x <4 x float>] addrspace(3)* @lds.v4, i32 0, i32 %x.i
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%val0 = load <4 x float>, <4 x float> addrspace(3)* %arrayidx0, align 4
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%elt0 = extractelement <4 x float> %val0, i32 0
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%elt1 = extractelement <4 x float> %val0, i32 1
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%elt2 = extractelement <4 x float> %val0, i32 2
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%elt3 = extractelement <4 x float> %val0, i32 3
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%add0 = fadd float %elt0, %elt2
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%add1 = fadd float %elt1, %elt3
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%add2 = fadd float %add0, %add1
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%out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
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store float %add2, float addrspace(1)* %out.gep
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ret void
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}
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; FIXME: the v_lshl_b64 x, x, 32 is a bad way of doing a copy
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; CI-LABEL: {{^}}simple_read2_v3f32_superreg_align4:
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_X:[0-9]+]]:[[REG_Y:[0-9]+]]{{\]}}, v{{[0-9]+}} offset1:1{{$}}
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; CI-DAG: ds_read_b32 v[[REG_Z:[0-9]+]], v{{[0-9]+}} offset:8{{$}}
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; CI: v_lshr_b64 v{{\[}}[[Y_COPY:[0-9]+]]:{{[0-9]+\]}}, v{{\[}}[[REG_X]]:[[REG_Y]]{{\]}}, 32
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; CI-DAG: v_add_f32_e32 v[[ADD0:[0-9]+]], v[[REG_Z]], v[[REG_X]]
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; CI-DAG: v_add_f32_e32 v[[ADD1:[0-9]+]], v[[Y_COPY]], v[[ADD0]]
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; CI: buffer_store_dword v[[ADD1]]
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; CI: s_endpgm
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define void @simple_read2_v3f32_superreg_align4(float addrspace(1)* %out) #0 {
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%x.i = tail call i32 @llvm.r600.read.tidig.x() #1
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%arrayidx0 = getelementptr inbounds [512 x <3 x float>], [512 x <3 x float>] addrspace(3)* @lds.v3, i32 0, i32 %x.i
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%val0 = load <3 x float>, <3 x float> addrspace(3)* %arrayidx0, align 4
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%elt0 = extractelement <3 x float> %val0, i32 0
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%elt1 = extractelement <3 x float> %val0, i32 1
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%elt2 = extractelement <3 x float> %val0, i32 2
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%add0 = fadd float %elt0, %elt2
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%add1 = fadd float %add0, %elt1
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%out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
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store float %add1, float addrspace(1)* %out.gep
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ret void
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}
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; CI-LABEL: {{^}}simple_read2_v4f32_superreg_align8:
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_W:[0-9]+]]:[[REG_Z:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:3 offset1:2{{$}}
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_X:[0-9]+]]:[[REG_Y:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:1{{$}}
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; CI: buffer_store_dwordx4
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; CI: s_endpgm
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define void @simple_read2_v4f32_superreg_align8(<4 x float> addrspace(1)* %out) #0 {
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%x.i = tail call i32 @llvm.r600.read.tidig.x() #1
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%arrayidx0 = getelementptr inbounds [512 x <4 x float>], [512 x <4 x float>] addrspace(3)* @lds.v4, i32 0, i32 %x.i
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%val0 = load <4 x float>, <4 x float> addrspace(3)* %arrayidx0, align 8
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%out.gep = getelementptr inbounds <4 x float>, <4 x float> addrspace(1)* %out, i32 %x.i
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store <4 x float> %val0, <4 x float> addrspace(1)* %out.gep
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ret void
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}
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; CI-LABEL: {{^}}simple_read2_v4f32_superreg:
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_W:[0-9]+]]:[[REG_Z:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:3 offset1:2{{$}}
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_X:[0-9]+]]:[[REG_Y:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:1{{$}}
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; CI: buffer_store_dwordx4
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; CI: s_endpgm
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define void @simple_read2_v4f32_superreg(<4 x float> addrspace(1)* %out) #0 {
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%x.i = tail call i32 @llvm.r600.read.tidig.x() #1
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%arrayidx0 = getelementptr inbounds [512 x <4 x float>], [512 x <4 x float>] addrspace(3)* @lds.v4, i32 0, i32 %x.i
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%val0 = load <4 x float>, <4 x float> addrspace(3)* %arrayidx0
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%out.gep = getelementptr inbounds <4 x float>, <4 x float> addrspace(1)* %out, i32 %x.i
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store <4 x float> %val0, <4 x float> addrspace(1)* %out.gep
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ret void
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}
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; CI-LABEL: {{^}}simple_read2_v8f32_superreg:
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT7:[0-9]+]]:[[REG_ELT6:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:7 offset1:6{{$}}
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT5:[0-9]+]]:[[REG_ELT4:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:5 offset1:4{{$}}
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT3:[0-9]+]]:[[REG_ELT2:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:3 offset1:2{{$}}
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT1:[0-9]+]]:[[REG_ELT0:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:1{{$}}
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; CI: buffer_store_dword
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; CI: buffer_store_dword
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; CI: buffer_store_dword
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; CI: buffer_store_dword
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; CI: buffer_store_dword
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; CI: buffer_store_dword
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; CI: buffer_store_dword
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; CI: buffer_store_dword
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; CI: s_endpgm
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define void @simple_read2_v8f32_superreg(<8 x float> addrspace(1)* %out) #0 {
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%x.i = tail call i32 @llvm.r600.read.tidig.x() #1
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%arrayidx0 = getelementptr inbounds [512 x <8 x float>], [512 x <8 x float>] addrspace(3)* @lds.v8, i32 0, i32 %x.i
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%val0 = load <8 x float>, <8 x float> addrspace(3)* %arrayidx0
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%out.gep = getelementptr inbounds <8 x float>, <8 x float> addrspace(1)* %out, i32 %x.i
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store <8 x float> %val0, <8 x float> addrspace(1)* %out.gep
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ret void
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}
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; CI-LABEL: {{^}}simple_read2_v16f32_superreg:
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT7:[0-9]+]]:[[REG_ELT6:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:15 offset1:14{{$}}
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; CI-NOT: v_mov_b32
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT7:[0-9]+]]:[[REG_ELT6:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:13 offset1:12{{$}}
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; CI-NOT: v_mov_b32
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT7:[0-9]+]]:[[REG_ELT6:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:11 offset1:10{{$}}
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; CI-NOT: v_mov_b32
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT7:[0-9]+]]:[[REG_ELT6:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:9 offset1:8{{$}}
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; CI-NOT: v_mov_b32
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT7:[0-9]+]]:[[REG_ELT6:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:7 offset1:6{{$}}
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; CI-NOT: v_mov_b32
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT5:[0-9]+]]:[[REG_ELT4:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:5 offset1:4{{$}}
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; CI-NOT: v_mov_b32
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT3:[0-9]+]]:[[REG_ELT2:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:3 offset1:2{{$}}
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; CI-NOT: v_mov_b32
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT1:[0-9]+]]:[[REG_ELT0:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:1{{$}}
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; CI-NOT: v_mov_b32
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; CI: s_waitcnt lgkmcnt(0)
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; CI: buffer_store_dword
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; CI: buffer_store_dword
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; CI: buffer_store_dword
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; CI: buffer_store_dword
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; CI: buffer_store_dword
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; CI: buffer_store_dword
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; CI: buffer_store_dword
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; CI: buffer_store_dword
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; CI: buffer_store_dword
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; CI: buffer_store_dword
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; CI: buffer_store_dword
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; CI: buffer_store_dword
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; CI: buffer_store_dword
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; CI: buffer_store_dword
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; CI: buffer_store_dword
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; CI: buffer_store_dword
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; CI: s_endpgm
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define void @simple_read2_v16f32_superreg(<16 x float> addrspace(1)* %out) #0 {
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%x.i = tail call i32 @llvm.r600.read.tidig.x() #1
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%arrayidx0 = getelementptr inbounds [512 x <16 x float>], [512 x <16 x float>] addrspace(3)* @lds.v16, i32 0, i32 %x.i
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%val0 = load <16 x float>, <16 x float> addrspace(3)* %arrayidx0
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%out.gep = getelementptr inbounds <16 x float>, <16 x float> addrspace(1)* %out, i32 %x.i
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store <16 x float> %val0, <16 x float> addrspace(1)* %out.gep
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ret void
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}
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; Do scalar loads into the super register we need.
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; CI-LABEL: {{^}}simple_read2_v2f32_superreg_scalar_loads_align4:
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT0:[0-9]+]]:[[REG_ELT1:[0-9]+]]{{\]}}, v{{[0-9]+}} offset1:1{{$}}
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; CI-NOT: v_mov
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; CI: buffer_store_dwordx2 v{{\[}}[[REG_ELT0]]:[[REG_ELT1]]{{\]}}
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; CI: s_endpgm
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define void @simple_read2_v2f32_superreg_scalar_loads_align4(<2 x float> addrspace(1)* %out) #0 {
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%x.i = tail call i32 @llvm.r600.read.tidig.x() #1
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%arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
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%arrayidx1 = getelementptr inbounds float, float addrspace(3)* %arrayidx0, i32 1
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%val0 = load float, float addrspace(3)* %arrayidx0
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%val1 = load float, float addrspace(3)* %arrayidx1
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%vec.0 = insertelement <2 x float> undef, float %val0, i32 0
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%vec.1 = insertelement <2 x float> %vec.0, float %val1, i32 1
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%out.gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %out, i32 %x.i
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store <2 x float> %vec.1, <2 x float> addrspace(1)* %out.gep
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ret void
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}
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; Do scalar loads into the super register we need.
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; CI-LABEL: {{^}}simple_read2_v4f32_superreg_scalar_loads_align4:
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT0:[0-9]+]]:[[REG_ELT1:[0-9]+]]{{\]}}, v{{[0-9]+}} offset1:1{{$}}
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT2:[0-9]+]]:[[REG_ELT3:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:2 offset1:3{{$}}
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; CI-NOT: v_mov
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; CI: buffer_store_dwordx4 v{{\[}}[[REG_ELT0]]:[[REG_ELT3]]{{\]}}
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; CI: s_endpgm
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define void @simple_read2_v4f32_superreg_scalar_loads_align4(<4 x float> addrspace(1)* %out) #0 {
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%x.i = tail call i32 @llvm.r600.read.tidig.x() #1
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%arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
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%arrayidx1 = getelementptr inbounds float, float addrspace(3)* %arrayidx0, i32 1
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%arrayidx2 = getelementptr inbounds float, float addrspace(3)* %arrayidx0, i32 2
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%arrayidx3 = getelementptr inbounds float, float addrspace(3)* %arrayidx0, i32 3
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%val0 = load float, float addrspace(3)* %arrayidx0
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%val1 = load float, float addrspace(3)* %arrayidx1
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%val2 = load float, float addrspace(3)* %arrayidx2
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%val3 = load float, float addrspace(3)* %arrayidx3
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%vec.0 = insertelement <4 x float> undef, float %val0, i32 0
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%vec.1 = insertelement <4 x float> %vec.0, float %val1, i32 1
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%vec.2 = insertelement <4 x float> %vec.1, float %val2, i32 2
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%vec.3 = insertelement <4 x float> %vec.2, float %val3, i32 3
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%out.gep = getelementptr inbounds <4 x float>, <4 x float> addrspace(1)* %out, i32 %x.i
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store <4 x float> %vec.3, <4 x float> addrspace(1)* %out.gep
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ret void
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}
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; Function Attrs: nounwind readnone
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declare i32 @llvm.r600.read.tgid.x() #1
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; Function Attrs: nounwind readnone
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declare i32 @llvm.r600.read.tgid.y() #1
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; Function Attrs: nounwind readnone
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declare i32 @llvm.r600.read.tidig.x() #1
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; Function Attrs: nounwind readnone
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declare i32 @llvm.r600.read.tidig.y() #1
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; Function Attrs: noduplicate nounwind
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declare void @llvm.AMDGPU.barrier.local() #2
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attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
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attributes #1 = { nounwind readnone }
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attributes #2 = { noduplicate nounwind }
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