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108 lines
4.4 KiB
TableGen
108 lines
4.4 KiB
TableGen
//=- HexagonInstrInfoV3.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the Hexagon V3 instructions in TableGen format.
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//
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//===----------------------------------------------------------------------===//
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def callv3 : SDNode<"HexagonISD::CALLv3", SDT_SPCall,
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[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
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def callv3nr : SDNode<"HexagonISD::CALLv3nr", SDT_SPCall,
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[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
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//===----------------------------------------------------------------------===//
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// J +
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//===----------------------------------------------------------------------===//
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// Call subroutine.
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let isCall = 1, neverHasSideEffects = 1,
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Defs = [D0, D1, D2, D3, D4, D5, D6, D7, R28, R31,
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P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
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def CALLv3 : JInst<(outs), (ins calltarget:$dst),
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"call $dst", []>, Requires<[HasV3T]>;
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}
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//===----------------------------------------------------------------------===//
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// J -
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// JR +
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//===----------------------------------------------------------------------===//
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// Call subroutine from register.
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let isCall = 1, neverHasSideEffects = 1,
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Defs = [D0, D1, D2, D3, D4, D5, D6, D7, R28, R31,
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P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
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def CALLRv3 : JRInst<(outs), (ins IntRegs:$dst),
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"callr $dst",
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[]>, Requires<[HasV3TOnly]>;
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}
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//===----------------------------------------------------------------------===//
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// JR -
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// ALU64/ALU +
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//===----------------------------------------------------------------------===//
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let AddedComplexity = 200 in
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def MAXw_dd : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
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DoubleRegs:$src2),
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"$dst = max($src2, $src1)",
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[(set (i64 DoubleRegs:$dst),
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(i64 (select (i1 (setlt (i64 DoubleRegs:$src2),
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(i64 DoubleRegs:$src1))),
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(i64 DoubleRegs:$src1),
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(i64 DoubleRegs:$src2))))]>,
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Requires<[HasV3T]>;
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let AddedComplexity = 200 in
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def MINw_dd : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
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DoubleRegs:$src2),
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"$dst = min($src2, $src1)",
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[(set (i64 DoubleRegs:$dst),
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(i64 (select (i1 (setgt (i64 DoubleRegs:$src2),
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(i64 DoubleRegs:$src1))),
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(i64 DoubleRegs:$src1),
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(i64 DoubleRegs:$src2))))]>,
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Requires<[HasV3T]>;
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//===----------------------------------------------------------------------===//
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// ALU64/ALU -
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//===----------------------------------------------------------------------===//
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//def : Pat <(brcond (i1 (seteq (i32 IntRegs:$src1), 0)), bb:$offset),
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// (JMP_RegEzt (i32 IntRegs:$src1), bb:$offset)>, Requires<[HasV3T]>;
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//def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), 0)), bb:$offset),
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// (JMP_RegNzt (i32 IntRegs:$src1), bb:$offset)>, Requires<[HasV3T]>;
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//def : Pat <(brcond (i1 (setle (i32 IntRegs:$src1), 0)), bb:$offset),
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// (JMP_RegLezt (i32 IntRegs:$src1), bb:$offset)>, Requires<[HasV3T]>;
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//def : Pat <(brcond (i1 (setge (i32 IntRegs:$src1), 0)), bb:$offset),
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// (JMP_RegGezt (i32 IntRegs:$src1), bb:$offset)>, Requires<[HasV3T]>;
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//def : Pat <(brcond (i1 (setgt (i32 IntRegs:$src1), -1)), bb:$offset),
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// (JMP_RegGezt (i32 IntRegs:$src1), bb:$offset)>, Requires<[HasV3T]>;
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// Map call instruction
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def : Pat<(call (i32 IntRegs:$dst)),
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(CALLRv3 (i32 IntRegs:$dst))>, Requires<[HasV3T]>;
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def : Pat<(call tglobaladdr:$dst),
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(CALLv3 tglobaladdr:$dst)>, Requires<[HasV3T]>;
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def : Pat<(call texternalsym:$dst),
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(CALLv3 texternalsym:$dst)>, Requires<[HasV3T]>;
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