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eac3acc854
SGPRs are spilled into VGPRs using the {READ,WRITE}LANE_B32 instructions.
v2:
- Fix encoding of Lane Mask
- Use correct register flags, so we don't overwrite the low dword
when restoring multi-dword registers.
v3:
- Register spilling seems to hang the GPU, so replace all shaders
that need spilling with a dummy shader.
v4:
- Fix *LANE definitions
- Change destination reg class for 32-bit SMRD instructions
v5:
- Remove small optimization that was crashing Serious Sam 3.
https://bugs.freedesktop.org/show_bug.cgi?id=68224
https://bugs.freedesktop.org/show_bug.cgi?id=71285
NOTE: This is a candidate for the 3.4 branch.
llvm-svn: 195880
213 lines
9.2 KiB
C++
213 lines
9.2 KiB
C++
//===-- AMDGPUInstrInfo.h - AMDGPU Instruction Information ------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief Contains the definition of a TargetInstrInfo class that is common
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/// to all AMD GPUs.
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//
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//===----------------------------------------------------------------------===//
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#ifndef AMDGPUINSTRUCTIONINFO_H
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#define AMDGPUINSTRUCTIONINFO_H
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#include "AMDGPUInstrInfo.h"
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#include "AMDGPURegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include <map>
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#define GET_INSTRINFO_HEADER
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#define GET_INSTRINFO_ENUM
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#define GET_INSTRINFO_OPERAND_ENUM
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#include "AMDGPUGenInstrInfo.inc"
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#define OPCODE_IS_ZERO_INT AMDGPU::PRED_SETE_INT
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#define OPCODE_IS_NOT_ZERO_INT AMDGPU::PRED_SETNE_INT
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#define OPCODE_IS_ZERO AMDGPU::PRED_SETE
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#define OPCODE_IS_NOT_ZERO AMDGPU::PRED_SETNE
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namespace llvm {
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class AMDGPUTargetMachine;
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class MachineFunction;
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class MachineInstr;
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class MachineInstrBuilder;
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class AMDGPUInstrInfo : public AMDGPUGenInstrInfo {
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private:
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const AMDGPURegisterInfo RI;
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bool getNextBranchInstr(MachineBasicBlock::iterator &iter,
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MachineBasicBlock &MBB) const;
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virtual void anchor();
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protected:
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TargetMachine &TM;
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public:
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explicit AMDGPUInstrInfo(TargetMachine &tm);
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virtual const AMDGPURegisterInfo &getRegisterInfo() const = 0;
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bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
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unsigned &DstReg, unsigned &SubIdx) const;
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unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
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unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
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int &FrameIndex) const;
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bool hasLoadFromStackSlot(const MachineInstr *MI,
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const MachineMemOperand *&MMO,
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int &FrameIndex) const;
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unsigned isStoreFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
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unsigned isStoreFromStackSlotPostFE(const MachineInstr *MI,
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int &FrameIndex) const;
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bool hasStoreFromStackSlot(const MachineInstr *MI,
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const MachineMemOperand *&MMO,
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int &FrameIndex) const;
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MachineInstr *
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convertToThreeAddress(MachineFunction::iterator &MFI,
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MachineBasicBlock::iterator &MBBI,
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LiveVariables *LV) const;
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virtual void copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const = 0;
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virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
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virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const;
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virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const;
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protected:
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MachineInstr *foldMemoryOperandImpl(MachineFunction &MF,
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MachineInstr *MI,
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const SmallVectorImpl<unsigned> &Ops,
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int FrameIndex) const;
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MachineInstr *foldMemoryOperandImpl(MachineFunction &MF,
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MachineInstr *MI,
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const SmallVectorImpl<unsigned> &Ops,
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MachineInstr *LoadMI) const;
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/// \returns the smallest register index that will be accessed by an indirect
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/// read or write or -1 if indirect addressing is not used by this program.
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virtual int getIndirectIndexBegin(const MachineFunction &MF) const;
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/// \returns the largest register index that will be accessed by an indirect
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/// read or write or -1 if indirect addressing is not used by this program.
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virtual int getIndirectIndexEnd(const MachineFunction &MF) const;
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public:
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bool canFoldMemoryOperand(const MachineInstr *MI,
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const SmallVectorImpl<unsigned> &Ops) const;
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bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
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unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
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SmallVectorImpl<MachineInstr *> &NewMIs) const;
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bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
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SmallVectorImpl<SDNode *> &NewNodes) const;
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unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
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bool UnfoldLoad, bool UnfoldStore,
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unsigned *LoadRegIndex = 0) const;
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bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
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int64_t Offset1, int64_t Offset2,
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unsigned NumLoads) const;
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bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
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void insertNoop(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const;
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bool isPredicated(const MachineInstr *MI) const;
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bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
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const SmallVectorImpl<MachineOperand> &Pred2) const;
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bool DefinesPredicate(MachineInstr *MI,
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std::vector<MachineOperand> &Pred) const;
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bool isPredicable(MachineInstr *MI) const;
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bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
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// Helper functions that check the opcode for status information
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bool isLoadInst(llvm::MachineInstr *MI) const;
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bool isExtLoadInst(llvm::MachineInstr *MI) const;
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bool isSWSExtLoadInst(llvm::MachineInstr *MI) const;
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bool isSExtLoadInst(llvm::MachineInstr *MI) const;
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bool isZExtLoadInst(llvm::MachineInstr *MI) const;
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bool isAExtLoadInst(llvm::MachineInstr *MI) const;
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bool isStoreInst(llvm::MachineInstr *MI) const;
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bool isTruncStoreInst(llvm::MachineInstr *MI) const;
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bool isRegisterStore(const MachineInstr &MI) const;
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bool isRegisterLoad(const MachineInstr &MI) const;
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//===---------------------------------------------------------------------===//
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// Pure virtual funtions to be implemented by sub-classes.
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//===---------------------------------------------------------------------===//
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virtual unsigned getIEQOpcode() const = 0;
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virtual bool isMov(unsigned opcode) const = 0;
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/// \brief Calculate the "Indirect Address" for the given \p RegIndex and
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/// \p Channel
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///
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/// We model indirect addressing using a virtual address space that can be
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/// accesed with loads and stores. The "Indirect Address" is the memory
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/// address in this virtual address space that maps to the given \p RegIndex
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/// and \p Channel.
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virtual unsigned calculateIndirectAddress(unsigned RegIndex,
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unsigned Channel) const = 0;
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/// \returns The register class to be used for loading and storing values
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/// from an "Indirect Address" .
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virtual const TargetRegisterClass *getIndirectAddrRegClass() const = 0;
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/// \brief Build instruction(s) for an indirect register write.
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///
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/// \returns The instruction that performs the indirect register write
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virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator I,
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unsigned ValueReg, unsigned Address,
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unsigned OffsetReg) const = 0;
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/// \brief Build instruction(s) for an indirect register read.
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///
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/// \returns The instruction that performs the indirect register read
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virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator I,
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unsigned ValueReg, unsigned Address,
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unsigned OffsetReg) const = 0;
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/// \brief Convert the AMDIL MachineInstr to a supported ISA
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/// MachineInstr
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virtual void convertToISA(MachineInstr & MI, MachineFunction &MF,
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DebugLoc DL) const;
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/// \brief Build a MOV instruction.
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virtual MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator I,
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unsigned DstReg, unsigned SrcReg) const = 0;
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/// \brief Given a MIMG \p Opcode that writes all 4 channels, return the
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/// equivalent opcode that writes \p Channels Channels.
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int getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const;
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};
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namespace AMDGPU {
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int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex);
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} // End namespace AMDGPU
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} // End llvm namespace
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#define AMDGPU_FLAG_REGISTER_LOAD (UINT64_C(1) << 63)
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#define AMDGPU_FLAG_REGISTER_STORE (UINT64_C(1) << 62)
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#endif // AMDGPUINSTRINFO_H
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