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211ccabffb
This helps avoid redundant instructions to unpack, and repack the vectors. Ideally we could recognize that pattern and eliminate it. Currently v4i8 and other small element type vectors are scalarized, so this has the added bonus of avoiding that. llvm-svn: 213031
249 lines
8.9 KiB
C++
249 lines
8.9 KiB
C++
//===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief Interface definition of the TargetLowering class that is common
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/// to all AMD GPUs.
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//
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//===----------------------------------------------------------------------===//
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#ifndef AMDGPUISELLOWERING_H
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#define AMDGPUISELLOWERING_H
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#include "llvm/Target/TargetLowering.h"
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namespace llvm {
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class AMDGPUMachineFunction;
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class AMDGPUSubtarget;
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class MachineRegisterInfo;
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class AMDGPUTargetLowering : public TargetLowering {
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protected:
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const AMDGPUSubtarget *Subtarget;
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private:
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SDValue LowerConstantInitializer(const Constant* Init, const GlobalValue *GV,
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const SDValue &InitPtr,
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SDValue Chain,
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SelectionDAG &DAG) const;
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SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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/// \brief Lower vector stores by merging the vector elements into an integer
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/// of the same bitwidth.
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SDValue MergeVectorStore(const SDValue &Op, SelectionDAG &DAG) const;
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/// \brief Split a vector store into multiple scalar stores.
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/// \returns The resulting chain.
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SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSDIV24(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSDIV32(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSDIV64(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSREM(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSREM32(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSREM64(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
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SDValue ExpandSIGN_EXTEND_INREG(SDValue Op,
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unsigned BitsDiff,
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SelectionDAG &DAG) const;
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SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
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SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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protected:
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static EVT getEquivalentMemType(LLVMContext &Context, EVT VT);
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static EVT getEquivalentLoadRegType(LLVMContext &Context, EVT VT);
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/// \brief Helper function that adds Reg to the LiveIn list of the DAG's
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/// MachineFunction.
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///
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/// \returns a RegisterSDNode representing Reg.
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virtual SDValue CreateLiveInRegister(SelectionDAG &DAG,
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const TargetRegisterClass *RC,
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unsigned Reg, EVT VT) const;
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SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
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SelectionDAG &DAG) const;
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/// \brief Split a vector load into multiple scalar loads.
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SDValue SplitVectorLoad(const SDValue &Op, SelectionDAG &DAG) const;
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SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
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bool isHWTrueValue(SDValue Op) const;
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bool isHWFalseValue(SDValue Op) const;
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/// The SelectionDAGBuilder will automatically promote function arguments
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/// with illegal types. However, this does not work for the AMDGPU targets
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/// since the function arguments are stored in memory as these illegal types.
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/// In order to handle this properly we need to get the origianl types sizes
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/// from the LLVM IR Function and fixup the ISD:InputArg values before
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/// passing them to AnalyzeFormalArguments()
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void getOriginalFunctionArgs(SelectionDAG &DAG,
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const Function *F,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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SmallVectorImpl<ISD::InputArg> &OrigIns) const;
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void AnalyzeFormalArguments(CCState &State,
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const SmallVectorImpl<ISD::InputArg> &Ins) const;
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public:
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AMDGPUTargetLowering(TargetMachine &TM);
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bool isFAbsFree(EVT VT) const override;
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bool isFNegFree(EVT VT) const override;
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bool isTruncateFree(EVT Src, EVT Dest) const override;
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bool isTruncateFree(Type *Src, Type *Dest) const override;
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bool isZExtFree(Type *Src, Type *Dest) const override;
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bool isZExtFree(EVT Src, EVT Dest) const override;
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bool isZExtFree(SDValue Val, EVT VT2) const override;
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bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
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MVT getVectorIdxTy() const override;
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bool isSelectSupported(SelectSupportKind) const override;
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bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
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bool ShouldShrinkFPConstant(EVT VT) const override;
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bool isLoadBitCastBeneficial(EVT, EVT) const override;
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SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv,
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bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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SDLoc DL, SelectionDAG &DAG) const override;
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SDValue LowerCall(CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const override;
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SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
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void ReplaceNodeResults(SDNode * N,
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SmallVectorImpl<SDValue> &Results,
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SelectionDAG &DAG) const override;
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SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const;
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SDValue CombineMinMax(SDNode *N, SelectionDAG &DAG) const;
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const char* getTargetNodeName(unsigned Opcode) const override;
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virtual SDNode *PostISelFolding(MachineSDNode *N,
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SelectionDAG &DAG) const {
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return N;
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}
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/// \brief Determine which of the bits specified in \p Mask are known to be
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/// either zero or one and return them in the \p KnownZero and \p KnownOne
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/// bitsets.
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void computeKnownBitsForTargetNode(const SDValue Op,
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APInt &KnownZero,
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APInt &KnownOne,
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const SelectionDAG &DAG,
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unsigned Depth = 0) const override;
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virtual unsigned ComputeNumSignBitsForTargetNode(
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SDValue Op,
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const SelectionDAG &DAG,
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unsigned Depth = 0) const override;
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};
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namespace AMDGPUISD {
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enum {
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// AMDIL ISD Opcodes
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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CALL, // Function call based on a single integer
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UMUL, // 32bit unsigned multiplication
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RET_FLAG,
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BRANCH_COND,
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// End AMDIL ISD Opcodes
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DWORDADDR,
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FRACT,
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CLAMP,
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// SIN_HW, COS_HW - f32 for SI, 1 ULP max error, valid from -100 pi to 100 pi.
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// Denormals handled on some parts.
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COS_HW,
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SIN_HW,
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FMAX,
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SMAX,
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UMAX,
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FMIN,
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SMIN,
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UMIN,
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URECIP,
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DIV_SCALE,
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DIV_FMAS,
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DIV_FIXUP,
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TRIG_PREOP, // 1 ULP max error for f64
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// RCP, RSQ - For f32, 1 ULP max error, no denormal handling.
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// For f64, max error 2^29 ULP, handles denormals.
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RCP,
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RSQ,
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RSQ_LEGACY,
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RSQ_CLAMPED,
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DOT4,
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BFE_U32, // Extract range of bits with zero extension to 32-bits.
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BFE_I32, // Extract range of bits with sign extension to 32-bits.
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BFI, // (src0 & src1) | (~src0 & src2)
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BFM, // Insert a range of bits into a 32-bit word.
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BREV, // Reverse bits.
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MUL_U24,
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MUL_I24,
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MAD_U24,
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MAD_I24,
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TEXTURE_FETCH,
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EXPORT,
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CONST_ADDRESS,
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REGISTER_LOAD,
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REGISTER_STORE,
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LOAD_INPUT,
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SAMPLE,
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SAMPLEB,
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SAMPLED,
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SAMPLEL,
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// These cvt_f32_ubyte* nodes need to remain consecutive and in order.
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CVT_F32_UBYTE0,
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CVT_F32_UBYTE1,
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CVT_F32_UBYTE2,
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CVT_F32_UBYTE3,
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/// This node is for VLIW targets and it is used to represent a vector
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/// that is stored in consecutive registers with the same channel.
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/// For example:
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/// |X |Y|Z|W|
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/// T0|v.x| | | |
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/// T1|v.y| | | |
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/// T2|v.z| | | |
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/// T3|v.w| | | |
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BUILD_VERTICAL_VECTOR,
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FIRST_MEM_OPCODE_NUMBER = ISD::FIRST_TARGET_MEMORY_OPCODE,
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STORE_MSKOR,
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LOAD_CONSTANT,
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TBUFFER_STORE_FORMAT,
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LAST_AMDGPU_ISD_NUMBER
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};
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} // End namespace AMDGPUISD
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} // End namespace llvm
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#endif // AMDGPUISELLOWERING_H
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