Pavel Iliin 5403bb4617 [AArch64] FMLA/FMLS patterns improvement. ... FMLA/FMLS f16 indexed patterns added. Fixes https://bugs.llvm.org/show_bug.cgi?id=45467 Removed redundant v2f32 vector_extract indexed pattern since Instruction Selection is able to match v4f32 instead.		2020-04-21 18:23:21 +01:00
..
Analysis	Require "target datalayout" to be at the beginning of an IR file.	2020-04-20 11:55:49 -07:00
Assembler	Recommit: DebugInfo: Fix rangesBaseAddress DICompileUnit bitcode serialization/deserialization	2020-04-20 17:29:04 -07:00
Bindings
Bitcode	[DebugInfo] Change DIEnumerator payload type from int64_t to APInt	2020-04-18 12:49:31 -07:00
BugPoint
CodeGen	[AArch64] FMLA/FMLS patterns improvement.	2020-04-21 18:23:21 +01:00
DebugInfo	[XRay] Change xray_instr_map sled addresses from absolute to PC relative for x86-64	2020-04-21 09:36:09 -07:00
Demangle
Examples
ExecutionEngine
Feature
FileCheck
Instrumentation
Integer
JitListener
Linker
LTO
MachineVerifier
MC	[MC][Bugfix] Remove redundant parameter for relaxInstruction	2020-04-21 11:06:55 +08:00
Object
ObjectYAML
Other
Reduce
SafepointIRVerifier
Support
SymbolRewriter
TableGen
ThinLTO/X86
tools	[DWARFDebugLine] Check for errors when parsing v2 file/dir lists	2020-04-21 16:55:36 +02:00
Transforms	[NFC][InstCombine] sub-of-negatible.ll: some more test cases	2020-04-21 20:14:09 +03:00
Unit
Verifier
YAMLParser
.clang-format
CMakeLists.txt
lit.cfg.py
lit.site.cfg.py.in
TestRunner.sh