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287 lines
11 KiB
C++
287 lines
11 KiB
C++
//==- llvm/CodeGen/MachineMemOperand.h - MachineMemOperand class -*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the declaration of the MachineMemOperand class, which is a
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// description of a memory reference. It is used to help track dependencies
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// in the backend.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_MACHINEMEMOPERAND_H
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#define LLVM_CODEGEN_MACHINEMEMOPERAND_H
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#include "llvm/ADT/BitmaskEnum.h"
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#include "llvm/ADT/PointerUnion.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/IR/Metadata.h"
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#include "llvm/IR/Value.h" // PointerLikeTypeTraits<Value*>
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#include "llvm/Support/AtomicOrdering.h"
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#include "llvm/Support/DataTypes.h"
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namespace llvm {
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class FoldingSetNodeID;
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class MDNode;
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class raw_ostream;
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class MachineFunction;
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class ModuleSlotTracker;
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/// This class contains a discriminated union of information about pointers in
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/// memory operands, relating them back to LLVM IR or to virtual locations (such
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/// as frame indices) that are exposed during codegen.
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struct MachinePointerInfo {
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/// This is the IR pointer value for the access, or it is null if unknown.
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/// If this is null, then the access is to a pointer in the default address
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/// space.
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PointerUnion<const Value *, const PseudoSourceValue *> V;
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/// Offset - This is an offset from the base Value*.
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int64_t Offset;
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explicit MachinePointerInfo(const Value *v = nullptr, int64_t offset = 0)
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: V(v), Offset(offset) {}
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explicit MachinePointerInfo(const PseudoSourceValue *v,
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int64_t offset = 0)
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: V(v), Offset(offset) {}
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MachinePointerInfo getWithOffset(int64_t O) const {
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if (V.isNull()) return MachinePointerInfo();
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if (V.is<const Value*>())
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return MachinePointerInfo(V.get<const Value*>(), Offset+O);
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return MachinePointerInfo(V.get<const PseudoSourceValue*>(), Offset+O);
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}
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/// Return the LLVM IR address space number that this pointer points into.
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unsigned getAddrSpace() const;
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/// Return a MachinePointerInfo record that refers to the constant pool.
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static MachinePointerInfo getConstantPool(MachineFunction &MF);
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/// Return a MachinePointerInfo record that refers to the specified
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/// FrameIndex.
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static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI,
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int64_t Offset = 0);
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/// Return a MachinePointerInfo record that refers to a jump table entry.
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static MachinePointerInfo getJumpTable(MachineFunction &MF);
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/// Return a MachinePointerInfo record that refers to a GOT entry.
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static MachinePointerInfo getGOT(MachineFunction &MF);
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/// Stack pointer relative access.
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static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset);
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};
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//===----------------------------------------------------------------------===//
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/// A description of a memory reference used in the backend.
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/// Instead of holding a StoreInst or LoadInst, this class holds the address
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/// Value of the reference along with a byte size and offset. This allows it
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/// to describe lowered loads and stores. Also, the special PseudoSourceValue
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/// objects can be used to represent loads and stores to memory locations
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/// that aren't explicit in the regular LLVM IR.
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///
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class MachineMemOperand {
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public:
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/// Flags values. These may be or'd together.
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enum Flags : uint16_t {
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// No flags set.
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MONone = 0,
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/// The memory access reads data.
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MOLoad = 1u << 0,
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/// The memory access writes data.
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MOStore = 1u << 1,
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/// The memory access is volatile.
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MOVolatile = 1u << 2,
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/// The memory access is non-temporal.
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MONonTemporal = 1u << 3,
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/// The memory access is dereferenceable (i.e., doesn't trap).
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MODereferenceable = 1u << 4,
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/// The memory access always returns the same value (or traps).
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MOInvariant = 1u << 5,
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// Reserved for use by target-specific passes.
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MOTargetFlag1 = 1u << 6,
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MOTargetFlag2 = 1u << 7,
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MOTargetFlag3 = 1u << 8,
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LLVM_MARK_AS_BITMASK_ENUM(/* LargestFlag = */ MOTargetFlag3)
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};
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private:
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/// Atomic information for this memory operation.
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struct MachineAtomicInfo {
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/// Synchronization scope for this memory operation.
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unsigned SynchScope : 1; // enum SynchronizationScope
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/// Atomic ordering requirements for this memory operation. For cmpxchg
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/// atomic operations, atomic ordering requirements when store occurs.
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unsigned Ordering : 4; // enum AtomicOrdering
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/// For cmpxchg atomic operations, atomic ordering requirements when store
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/// does not occur.
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unsigned FailureOrdering : 4; // enum AtomicOrdering
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};
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MachinePointerInfo PtrInfo;
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uint64_t Size;
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Flags FlagVals;
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uint16_t BaseAlignLog2; // log_2(base_alignment) + 1
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MachineAtomicInfo AtomicInfo;
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AAMDNodes AAInfo;
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const MDNode *Ranges;
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public:
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/// Construct a MachineMemOperand object with the specified PtrInfo, flags,
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/// size, and base alignment. For atomic operations the synchronization scope
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/// and atomic ordering requirements must also be specified. For cmpxchg
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/// atomic operations the atomic ordering requirements when store does not
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/// occur must also be specified.
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MachineMemOperand(MachinePointerInfo PtrInfo, Flags flags, uint64_t s,
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unsigned base_alignment,
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const AAMDNodes &AAInfo = AAMDNodes(),
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const MDNode *Ranges = nullptr,
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SynchronizationScope SynchScope = CrossThread,
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AtomicOrdering Ordering = AtomicOrdering::NotAtomic,
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AtomicOrdering FailureOrdering = AtomicOrdering::NotAtomic);
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const MachinePointerInfo &getPointerInfo() const { return PtrInfo; }
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/// Return the base address of the memory access. This may either be a normal
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/// LLVM IR Value, or one of the special values used in CodeGen.
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/// Special values are those obtained via
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/// PseudoSourceValue::getFixedStack(int), PseudoSourceValue::getStack, and
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/// other PseudoSourceValue member functions which return objects which stand
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/// for frame/stack pointer relative references and other special references
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/// which are not representable in the high-level IR.
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const Value *getValue() const { return PtrInfo.V.dyn_cast<const Value*>(); }
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const PseudoSourceValue *getPseudoValue() const {
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return PtrInfo.V.dyn_cast<const PseudoSourceValue*>();
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}
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const void *getOpaqueValue() const { return PtrInfo.V.getOpaqueValue(); }
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/// Return the raw flags of the source value, \see Flags.
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Flags getFlags() const { return FlagVals; }
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/// Bitwise OR the current flags with the given flags.
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void setFlags(Flags f) { FlagVals |= f; }
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/// For normal values, this is a byte offset added to the base address.
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/// For PseudoSourceValue::FPRel values, this is the FrameIndex number.
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int64_t getOffset() const { return PtrInfo.Offset; }
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unsigned getAddrSpace() const { return PtrInfo.getAddrSpace(); }
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/// Return the size in bytes of the memory reference.
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uint64_t getSize() const { return Size; }
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/// Return the minimum known alignment in bytes of the actual memory
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/// reference.
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uint64_t getAlignment() const;
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/// Return the minimum known alignment in bytes of the base address, without
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/// the offset.
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uint64_t getBaseAlignment() const { return (1u << BaseAlignLog2) >> 1; }
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/// Return the AA tags for the memory reference.
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AAMDNodes getAAInfo() const { return AAInfo; }
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/// Return the range tag for the memory reference.
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const MDNode *getRanges() const { return Ranges; }
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/// Return the synchronization scope for this memory operation.
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SynchronizationScope getSynchScope() const {
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return static_cast<SynchronizationScope>(AtomicInfo.SynchScope);
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}
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/// Return the atomic ordering requirements for this memory operation. For
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/// cmpxchg atomic operations, return the atomic ordering requirements when
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/// store occurs.
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AtomicOrdering getOrdering() const {
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return static_cast<AtomicOrdering>(AtomicInfo.Ordering);
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}
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/// For cmpxchg atomic operations, return the atomic ordering requirements
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/// when store does not occur.
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AtomicOrdering getFailureOrdering() const {
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return static_cast<AtomicOrdering>(AtomicInfo.FailureOrdering);
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}
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bool isLoad() const { return FlagVals & MOLoad; }
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bool isStore() const { return FlagVals & MOStore; }
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bool isVolatile() const { return FlagVals & MOVolatile; }
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bool isNonTemporal() const { return FlagVals & MONonTemporal; }
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bool isDereferenceable() const { return FlagVals & MODereferenceable; }
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bool isInvariant() const { return FlagVals & MOInvariant; }
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/// Returns true if this operation has an atomic ordering requirement of
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/// unordered or higher, false otherwise.
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bool isAtomic() const { return getOrdering() != AtomicOrdering::NotAtomic; }
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/// Returns true if this memory operation doesn't have any ordering
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/// constraints other than normal aliasing. Volatile and atomic memory
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/// operations can't be reordered.
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///
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/// Currently, we don't model the difference between volatile and atomic
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/// operations. They should retain their ordering relative to all memory
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/// operations.
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bool isUnordered() const { return !isVolatile(); }
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/// Update this MachineMemOperand to reflect the alignment of MMO, if it has a
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/// greater alignment. This must only be used when the new alignment applies
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/// to all users of this MachineMemOperand.
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void refineAlignment(const MachineMemOperand *MMO);
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/// Change the SourceValue for this MachineMemOperand. This should only be
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/// used when an object is being relocated and all references to it are being
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/// updated.
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void setValue(const Value *NewSV) { PtrInfo.V = NewSV; }
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void setValue(const PseudoSourceValue *NewSV) { PtrInfo.V = NewSV; }
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void setOffset(int64_t NewOffset) { PtrInfo.Offset = NewOffset; }
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/// Profile - Gather unique data for the object.
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///
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void Profile(FoldingSetNodeID &ID) const;
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/// Support for operator<<.
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/// @{
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void print(raw_ostream &OS) const;
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void print(raw_ostream &OS, ModuleSlotTracker &MST) const;
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/// @}
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friend bool operator==(const MachineMemOperand &LHS,
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const MachineMemOperand &RHS) {
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return LHS.getValue() == RHS.getValue() &&
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LHS.getPseudoValue() == RHS.getPseudoValue() &&
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LHS.getSize() == RHS.getSize() &&
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LHS.getOffset() == RHS.getOffset() &&
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LHS.getFlags() == RHS.getFlags() &&
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LHS.getAAInfo() == RHS.getAAInfo() &&
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LHS.getRanges() == RHS.getRanges() &&
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LHS.getAlignment() == RHS.getAlignment() &&
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LHS.getAddrSpace() == RHS.getAddrSpace();
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}
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friend bool operator!=(const MachineMemOperand &LHS,
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const MachineMemOperand &RHS) {
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return !(LHS == RHS);
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}
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};
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inline raw_ostream &operator<<(raw_ostream &OS, const MachineMemOperand &MRO) {
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MRO.print(OS);
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return OS;
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}
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} // End llvm namespace
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#endif
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