Simon Pilgrim 436c202090 [CostModel][X86] Adjust fptosi/fptoui SSE/AVX legalized costs based on llvm-mca reports. ... Update (mainly) vXf32/vXf64 -> vXi8/vXi16 fptosi/fptoui costs based on the worst case costs from the script in D103695. Move to using legalized types wherever possible, which allows us to prune the cost tables.		2021-07-12 20:38:25 +01:00
..
abs.ll
aggregates.ll
alternate-shuffle-cost.ll
arith-fix.ll	[CostModel][X86] Adjust truncate SSE/AVX legalized costs based on llvm-mca reports.	2021-07-12 13:50:43 +01:00
arith-fma.ll
arith-fp.ll	[CostModel][X86] Improve AVX512 FDIV costs	2021-06-06 21:41:05 +01:00
arith-overflow.ll	[CostModel][X86] Adjust truncate SSE/AVX legalized costs based on llvm-mca reports.	2021-07-12 13:50:43 +01:00
arith-sminmax.ll
arith-ssat.ll
arith-uminmax.ll
arith-usat.ll
arith.ll	[CostModel][X86] Adjust truncate SSE/AVX legalized costs based on llvm-mca reports.	2021-07-12 13:50:43 +01:00
bitreverse.ll
bswap-store.ll	[X86] Improve costmodel for scalar byte swaps	2021-05-08 15:17:35 +03:00
bswap-vec.ll	[CostModel][X86] Add 512-bit bswap costs	2021-06-06 22:36:34 +01:00
bswap.ll	[X86] Improve costmodel for scalar byte swaps	2021-05-08 15:17:35 +03:00
cast.ll	[CostModel][X86] Adjust truncate SSE/AVX legalized costs based on llvm-mca reports.	2021-07-12 13:50:43 +01:00
costmodel.ll
ctlz.ll
ctpop.ll
cttz.ll
div.ll	[CostModel][X86] Improve accuracy of 256-bit non-uniform vector shifts on AVX1	2021-05-25 17:31:45 +01:00
extend.ll	[CostModel][X86] Adjust sext/zext SSE/AVX legalized costs based on llvm-mca reports.	2021-07-07 13:58:27 +01:00
fcmp.ll
fmaxnum-size-latency.ll
fmaxnum.ll
fminnum-size-latency.ll
fminnum.ll
fptosi.ll	[CostModel][X86] Adjust fptosi/fptoui SSE/AVX legalized costs based on llvm-mca reports.	2021-07-12 20:38:25 +01:00
fptoui.ll	[CostModel][X86] Adjust fptosi/fptoui SSE/AVX legalized costs based on llvm-mca reports.	2021-07-12 20:38:25 +01:00
free-intrinsics.ll
fround.ll
fshl.ll	[CostModel][X86] Improve accuracy of 256-bit non-uniform vector shifts on AVX1	2021-05-25 17:31:45 +01:00
fshr.ll	[CostModel][X86] Improve accuracy of 256-bit non-uniform vector shifts on AVX1	2021-05-25 17:31:45 +01:00
gep.ll
i32.ll
icmp.ll
insert-extract-at-zero-inseltpoison.ll	[CostModel][X86] Handle costs for insert/extractelement with non-immediate indices via stack	2021-07-05 13:26:53 +01:00
insert-extract-at-zero.ll	[CostModel][X86] Handle costs for insert/extractelement with non-immediate indices via stack	2021-07-05 13:26:53 +01:00
interleave-load-i32.ll
interleave-store-i32.ll
interleaved-load-float.ll
interleaved-load-i8.ll	Reland [X86] X86TTIImpl::getInterleavedMemoryOpCostAVX2(): use getMemoryOpCost()	2021-05-22 11:47:08 +03:00
interleaved-load-i16-stride-2.ll	[NFC][X86][Costmodel] Add some more interleaved load/store test with i16 element type	2021-05-26 21:55:37 +03:00
interleaved-load-i16-stride-3.ll	[NFC][X86][Costmodel] Add some more interleaved load/store test with i16 element type	2021-05-26 21:55:37 +03:00
interleaved-load-i16-stride-4.ll	[NFC][X86][Costmodel] Add some more interleaved load/store test with i16 element type	2021-05-26 21:55:37 +03:00
interleaved-load-i16-stride-5.ll	[NFC][X86][Costmodel] Add some more interleaved load/store test with i16 element type	2021-05-26 21:55:37 +03:00
interleaved-load-i16-stride-6.ll	[NFC][X86][Costmodel] Add some more interleaved load/store test with i16 element type	2021-05-26 21:55:37 +03:00
interleaved-load-store-double.ll
interleaved-load-store-i64.ll
interleaved-store-i8.ll	Reland [X86] X86TTIImpl::getInterleavedMemoryOpCostAVX2(): use getMemoryOpCost()	2021-05-22 11:47:08 +03:00
interleaved-store-i16-stride-2.ll	[NFC][X86][Costmodel] Add some more interleaved load/store test with i16 element type	2021-05-26 21:55:37 +03:00
interleaved-store-i16-stride-3.ll	[NFC][X86][Costmodel] Add some more interleaved load/store test with i16 element type	2021-05-26 21:55:37 +03:00
interleaved-store-i16-stride-4.ll	[NFC][X86][Costmodel] Add some more interleaved load/store test with i16 element type	2021-05-26 21:55:37 +03:00
interleaved-store-i16-stride-5.ll	[NFC][X86][Costmodel] Add some more interleaved load/store test with i16 element type	2021-05-26 21:55:37 +03:00
interleaved-store-i16-stride-6.ll	[NFC][X86][Costmodel] Add some more interleaved load/store test with i16 element type	2021-05-26 21:55:37 +03:00
intrinsic-cost-kinds.ll	[CostModel][X86] Adjust truncate SSE/AVX legalized costs based on llvm-mca reports.	2021-07-12 13:50:43 +01:00
intrinsic-cost.ll
lit.local.cfg
load_store.ll	Reland [X86][CostModel] X86TTIImpl::getMemoryOpCost(): rewrite vector handling again	2021-05-22 11:46:32 +03:00
load-bswap.ll	[X86] Improve costmodel for scalar byte swaps	2021-05-08 15:17:35 +03:00
logicalop.ll
loop_v2-inseltpoison.ll
loop_v2.ll
masked-intrinsic-cost-inseltpoison.ll	[CostModel][X86] Adjust sext/zext SSE/AVX legalized costs based on llvm-mca reports.	2021-07-07 13:58:27 +01:00
masked-intrinsic-cost.ll	[CostModel][X86] Adjust sext/zext SSE/AVX legalized costs based on llvm-mca reports.	2021-07-07 13:58:27 +01:00
min-legal-vector-width.ll	[CostModel][X86] Adjust truncate SSE/AVX legalized costs based on llvm-mca reports.	2021-07-12 13:50:43 +01:00
reduce-add.ll
reduce-and.ll
reduce-fadd.ll	[CostModel][X86] Improve v2f32 fadd reduction cost	2021-04-23 16:56:13 +01:00
reduce-fmax.ll
reduce-fmin.ll
reduce-fmul.ll	[CostModel][X86] Improve f64/v2f64/v4f64 FMUL costs on AVX1 targets to account for slower btver2	2021-05-21 18:12:13 +01:00
reduce-mul.ll	[CostModel][X86] Adjust sext/zext SSE/AVX legalized costs based on llvm-mca reports.	2021-07-07 13:58:27 +01:00
reduce-or.ll
reduce-smax.ll
reduce-smin.ll
reduce-umax.ll
reduce-umin.ll
reduce-xor.ll
reduction.ll	[TTI] Remove IsPairwiseForm from getArithmeticReductionCost	2021-07-09 11:51:16 +01:00
rem.ll	[CostModel][X86] Adjust truncate SSE/AVX legalized costs based on llvm-mca reports.	2021-07-12 13:50:43 +01:00
scalarize.ll
shuffle-broadcast.ll
shuffle-extract_subvector.ll
shuffle-insert_subvector.ll
shuffle-reverse.ll	[COST][X86]Improve cost model for reverse shuffle v32i16/v64i8 in AVX512F.	2021-04-27 11:14:21 -07:00
shuffle-select.ll
shuffle-single-src.ll
shuffle-transpose.ll
shuffle-two-src.ll
sitofp.ll	[CostModel][X86] Adjust sext/zext SSE/AVX legalized costs based on llvm-mca reports.	2021-07-07 13:58:27 +01:00
size-cost.ll
slm-arith-costs.ll	[CostModel][X86] Adjust truncate SSE/AVX legalized costs based on llvm-mca reports.	2021-07-12 13:50:43 +01:00
sse-itoi.ll	[CostModel][X86] Adjust truncate SSE/AVX legalized costs based on llvm-mca reports.	2021-07-12 13:50:43 +01:00
strided-load-i8.ll
strided-load-i16.ll
strided-load-i32.ll
strided-load-i64.ll
tiny.ll
trunc.ll	[CostModel][X86] Adjust truncate SSE/AVX legalized costs based on llvm-mca reports.	2021-07-12 13:50:43 +01:00
uitofp.ll	[CostModel][X86] Adjust sext/zext SSE/AVX legalized costs based on llvm-mca reports.	2021-07-07 13:58:27 +01:00
uniformshift-inseltpoison.ll
uniformshift.ll
vdiv-cost.ll
vector_gep-inseltpoison.ll
vector_gep.ll
vector-extract.ll	[CostModel][X86] Handle costs for insert/extractelement with non-immediate indices via stack	2021-07-05 13:26:53 +01:00
vector-insert-inseltpoison.ll	[CostModel][X86] Handle costs for insert/extractelement with non-immediate indices via stack	2021-07-05 13:26:53 +01:00
vector-insert.ll	[CostModel][X86] Handle costs for insert/extractelement with non-immediate indices via stack	2021-07-05 13:26:53 +01:00
vectorized-loop.ll	[CostModel][X86] Improve v8i32 MUL costs on AVX1 targets to account for slower btver2	2021-05-22 11:13:07 +01:00
vselect-cost.ll
vshift-ashr-cost-inseltpoison.ll	[CostModel][X86] Improve accuracy of 256-bit non-uniform vector shifts on AVX1	2021-05-25 17:31:45 +01:00
vshift-ashr-cost.ll	[CostModel][X86] Improve accuracy of 256-bit non-uniform vector shifts on AVX1	2021-05-25 17:31:45 +01:00
vshift-lshr-cost-inseltpoison.ll	[CostModel][X86] Improve accuracy of 256-bit non-uniform vector shifts on AVX1	2021-05-25 17:31:45 +01:00
vshift-lshr-cost.ll	[CostModel][X86] Improve accuracy of 256-bit non-uniform vector shifts on AVX1	2021-05-25 17:31:45 +01:00
vshift-shl-cost-inseltpoison.ll	[CostModel][X86] Improve accuracy of 256-bit non-uniform vector shifts on AVX1	2021-05-25 17:31:45 +01:00
vshift-shl-cost.ll	[CostModel][X86] Improve accuracy of 256-bit non-uniform vector shifts on AVX1	2021-05-25 17:31:45 +01:00