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llvm-mirror/test/CodeGen/Hexagon/intrinsics
Krzysztof Parzyszek 220ad04ad1 [Hexagon] Add intrinsics for data cache operations
This is the LLVM part, adding definitions for
  void @llvm.hexagon.Y2.dccleana(i8*)
  void @llvm.hexagon.Y2.dccleaninva(i8*)
  void @llvm.hexagon.Y2.dcinva(i8*)
  void @llvm.hexagon.Y2.dczeroa(i8*)
  void @llvm.hexagon.Y4.l2fetch(i8*, i32)
  void @llvm.hexagon.Y5.l2fetch(i8*, i64)
The clang part will follow.

llvm-svn: 308032
2017-07-14 15:58:48 +00:00
..
alu32_alu.ll
alu32_perm.ll
byte-store-double.ll [Hexagon] Add intrinsics for masked vector stores 2017-02-22 21:23:09 +00:00
byte-store.ll [Hexagon] Add intrinsics for masked vector stores 2017-02-22 21:23:09 +00:00
cr.ll
llsc_bundling.ll
system_user.ll [Hexagon] Add intrinsics for data cache operations 2017-07-14 15:58:48 +00:00
xtype_alu.ll
xtype_bit.ll
xtype_complex.ll
xtype_fp.ll
xtype_mpy.ll
xtype_perm.ll
xtype_pred.ll
xtype_shift.ll