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493 lines
16 KiB
C++
493 lines
16 KiB
C++
//===- DemandedBits.cpp - Determine demanded bits -------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass implements a demanded bits analysis. A demanded bit is one that
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// contributes to a result; bits that are not demanded can be either zero or
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// one without affecting control or data flow. For example in this sequence:
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//
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// %1 = add i32 %x, %y
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// %2 = trunc i32 %1 to i16
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//
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// Only the lowest 16 bits of %1 are demanded; the rest are removed by the
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// trunc.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Analysis/DemandedBits.h"
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#include "llvm/ADT/APInt.h"
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#include "llvm/ADT/SetVector.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/Analysis/AssumptionCache.h"
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#include "llvm/Analysis/ValueTracking.h"
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#include "llvm/IR/BasicBlock.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/IR/DerivedTypes.h"
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#include "llvm/IR/Dominators.h"
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#include "llvm/IR/InstIterator.h"
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#include "llvm/IR/InstrTypes.h"
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#include "llvm/IR/Instruction.h"
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#include "llvm/IR/IntrinsicInst.h"
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#include "llvm/IR/Intrinsics.h"
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#include "llvm/IR/Module.h"
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#include "llvm/IR/Operator.h"
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#include "llvm/IR/PassManager.h"
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#include "llvm/IR/PatternMatch.h"
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#include "llvm/IR/Type.h"
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#include "llvm/IR/Use.h"
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#include "llvm/Pass.h"
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#include "llvm/Support/Casting.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/KnownBits.h"
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#include "llvm/Support/raw_ostream.h"
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#include <algorithm>
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#include <cstdint>
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using namespace llvm;
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using namespace llvm::PatternMatch;
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#define DEBUG_TYPE "demanded-bits"
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char DemandedBitsWrapperPass::ID = 0;
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INITIALIZE_PASS_BEGIN(DemandedBitsWrapperPass, "demanded-bits",
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"Demanded bits analysis", false, false)
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INITIALIZE_PASS_DEPENDENCY(AssumptionCacheTracker)
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INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
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INITIALIZE_PASS_END(DemandedBitsWrapperPass, "demanded-bits",
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"Demanded bits analysis", false, false)
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DemandedBitsWrapperPass::DemandedBitsWrapperPass() : FunctionPass(ID) {
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initializeDemandedBitsWrapperPassPass(*PassRegistry::getPassRegistry());
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}
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void DemandedBitsWrapperPass::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesCFG();
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AU.addRequired<AssumptionCacheTracker>();
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AU.addRequired<DominatorTreeWrapperPass>();
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AU.setPreservesAll();
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}
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void DemandedBitsWrapperPass::print(raw_ostream &OS, const Module *M) const {
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DB->print(OS);
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}
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static bool isAlwaysLive(Instruction *I) {
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return I->isTerminator() || isa<DbgInfoIntrinsic>(I) || I->isEHPad() ||
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I->mayHaveSideEffects();
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}
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void DemandedBits::determineLiveOperandBits(
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const Instruction *UserI, const Value *Val, unsigned OperandNo,
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const APInt &AOut, APInt &AB, KnownBits &Known, KnownBits &Known2,
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bool &KnownBitsComputed) {
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unsigned BitWidth = AB.getBitWidth();
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// We're called once per operand, but for some instructions, we need to
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// compute known bits of both operands in order to determine the live bits of
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// either (when both operands are instructions themselves). We don't,
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// however, want to do this twice, so we cache the result in APInts that live
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// in the caller. For the two-relevant-operands case, both operand values are
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// provided here.
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auto ComputeKnownBits =
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[&](unsigned BitWidth, const Value *V1, const Value *V2) {
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if (KnownBitsComputed)
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return;
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KnownBitsComputed = true;
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const DataLayout &DL = UserI->getModule()->getDataLayout();
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Known = KnownBits(BitWidth);
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computeKnownBits(V1, Known, DL, 0, &AC, UserI, &DT);
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if (V2) {
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Known2 = KnownBits(BitWidth);
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computeKnownBits(V2, Known2, DL, 0, &AC, UserI, &DT);
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}
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};
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switch (UserI->getOpcode()) {
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default: break;
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case Instruction::Call:
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case Instruction::Invoke:
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if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(UserI))
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switch (II->getIntrinsicID()) {
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default: break;
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case Intrinsic::bswap:
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// The alive bits of the input are the swapped alive bits of
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// the output.
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AB = AOut.byteSwap();
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break;
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case Intrinsic::bitreverse:
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// The alive bits of the input are the reversed alive bits of
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// the output.
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AB = AOut.reverseBits();
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break;
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case Intrinsic::ctlz:
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if (OperandNo == 0) {
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// We need some output bits, so we need all bits of the
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// input to the left of, and including, the leftmost bit
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// known to be one.
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ComputeKnownBits(BitWidth, Val, nullptr);
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AB = APInt::getHighBitsSet(BitWidth,
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std::min(BitWidth, Known.countMaxLeadingZeros()+1));
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}
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break;
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case Intrinsic::cttz:
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if (OperandNo == 0) {
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// We need some output bits, so we need all bits of the
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// input to the right of, and including, the rightmost bit
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// known to be one.
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ComputeKnownBits(BitWidth, Val, nullptr);
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AB = APInt::getLowBitsSet(BitWidth,
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std::min(BitWidth, Known.countMaxTrailingZeros()+1));
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}
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break;
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case Intrinsic::fshl:
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case Intrinsic::fshr: {
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const APInt *SA;
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if (OperandNo == 2) {
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// Shift amount is modulo the bitwidth. For powers of two we have
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// SA % BW == SA & (BW - 1).
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if (isPowerOf2_32(BitWidth))
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AB = BitWidth - 1;
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} else if (match(II->getOperand(2), m_APInt(SA))) {
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// Normalize to funnel shift left. APInt shifts of BitWidth are well-
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// defined, so no need to special-case zero shifts here.
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uint64_t ShiftAmt = SA->urem(BitWidth);
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if (II->getIntrinsicID() == Intrinsic::fshr)
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ShiftAmt = BitWidth - ShiftAmt;
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if (OperandNo == 0)
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AB = AOut.lshr(ShiftAmt);
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else if (OperandNo == 1)
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AB = AOut.shl(BitWidth - ShiftAmt);
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}
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break;
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}
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}
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break;
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case Instruction::Add:
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case Instruction::Sub:
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case Instruction::Mul:
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// Find the highest live output bit. We don't need any more input
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// bits than that (adds, and thus subtracts, ripple only to the
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// left).
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AB = APInt::getLowBitsSet(BitWidth, AOut.getActiveBits());
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break;
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case Instruction::Shl:
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if (OperandNo == 0) {
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const APInt *ShiftAmtC;
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if (match(UserI->getOperand(1), m_APInt(ShiftAmtC))) {
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uint64_t ShiftAmt = ShiftAmtC->getLimitedValue(BitWidth - 1);
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AB = AOut.lshr(ShiftAmt);
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// If the shift is nuw/nsw, then the high bits are not dead
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// (because we've promised that they *must* be zero).
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const ShlOperator *S = cast<ShlOperator>(UserI);
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if (S->hasNoSignedWrap())
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AB |= APInt::getHighBitsSet(BitWidth, ShiftAmt+1);
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else if (S->hasNoUnsignedWrap())
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AB |= APInt::getHighBitsSet(BitWidth, ShiftAmt);
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}
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}
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break;
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case Instruction::LShr:
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if (OperandNo == 0) {
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const APInt *ShiftAmtC;
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if (match(UserI->getOperand(1), m_APInt(ShiftAmtC))) {
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uint64_t ShiftAmt = ShiftAmtC->getLimitedValue(BitWidth - 1);
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AB = AOut.shl(ShiftAmt);
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// If the shift is exact, then the low bits are not dead
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// (they must be zero).
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if (cast<LShrOperator>(UserI)->isExact())
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AB |= APInt::getLowBitsSet(BitWidth, ShiftAmt);
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}
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}
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break;
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case Instruction::AShr:
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if (OperandNo == 0) {
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const APInt *ShiftAmtC;
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if (match(UserI->getOperand(1), m_APInt(ShiftAmtC))) {
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uint64_t ShiftAmt = ShiftAmtC->getLimitedValue(BitWidth - 1);
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AB = AOut.shl(ShiftAmt);
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// Because the high input bit is replicated into the
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// high-order bits of the result, if we need any of those
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// bits, then we must keep the highest input bit.
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if ((AOut & APInt::getHighBitsSet(BitWidth, ShiftAmt))
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.getBoolValue())
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AB.setSignBit();
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// If the shift is exact, then the low bits are not dead
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// (they must be zero).
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if (cast<AShrOperator>(UserI)->isExact())
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AB |= APInt::getLowBitsSet(BitWidth, ShiftAmt);
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}
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}
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break;
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case Instruction::And:
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AB = AOut;
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// For bits that are known zero, the corresponding bits in the
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// other operand are dead (unless they're both zero, in which
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// case they can't both be dead, so just mark the LHS bits as
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// dead).
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ComputeKnownBits(BitWidth, UserI->getOperand(0), UserI->getOperand(1));
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if (OperandNo == 0)
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AB &= ~Known2.Zero;
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else
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AB &= ~(Known.Zero & ~Known2.Zero);
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break;
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case Instruction::Or:
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AB = AOut;
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// For bits that are known one, the corresponding bits in the
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// other operand are dead (unless they're both one, in which
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// case they can't both be dead, so just mark the LHS bits as
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// dead).
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ComputeKnownBits(BitWidth, UserI->getOperand(0), UserI->getOperand(1));
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if (OperandNo == 0)
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AB &= ~Known2.One;
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else
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AB &= ~(Known.One & ~Known2.One);
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break;
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case Instruction::Xor:
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case Instruction::PHI:
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AB = AOut;
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break;
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case Instruction::Trunc:
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AB = AOut.zext(BitWidth);
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break;
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case Instruction::ZExt:
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AB = AOut.trunc(BitWidth);
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break;
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case Instruction::SExt:
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AB = AOut.trunc(BitWidth);
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// Because the high input bit is replicated into the
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// high-order bits of the result, if we need any of those
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// bits, then we must keep the highest input bit.
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if ((AOut & APInt::getHighBitsSet(AOut.getBitWidth(),
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AOut.getBitWidth() - BitWidth))
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.getBoolValue())
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AB.setSignBit();
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break;
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case Instruction::Select:
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if (OperandNo != 0)
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AB = AOut;
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break;
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case Instruction::ExtractElement:
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if (OperandNo == 0)
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AB = AOut;
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break;
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case Instruction::InsertElement:
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case Instruction::ShuffleVector:
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if (OperandNo == 0 || OperandNo == 1)
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AB = AOut;
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break;
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}
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}
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bool DemandedBitsWrapperPass::runOnFunction(Function &F) {
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auto &AC = getAnalysis<AssumptionCacheTracker>().getAssumptionCache(F);
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auto &DT = getAnalysis<DominatorTreeWrapperPass>().getDomTree();
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DB.emplace(F, AC, DT);
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return false;
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}
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void DemandedBitsWrapperPass::releaseMemory() {
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DB.reset();
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}
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void DemandedBits::performAnalysis() {
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if (Analyzed)
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// Analysis already completed for this function.
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return;
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Analyzed = true;
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Visited.clear();
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AliveBits.clear();
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DeadUses.clear();
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SmallSetVector<Instruction*, 16> Worklist;
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// Collect the set of "root" instructions that are known live.
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for (Instruction &I : instructions(F)) {
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if (!isAlwaysLive(&I))
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continue;
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LLVM_DEBUG(dbgs() << "DemandedBits: Root: " << I << "\n");
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// For integer-valued instructions, set up an initial empty set of alive
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// bits and add the instruction to the work list. For other instructions
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// add their operands to the work list (for integer values operands, mark
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// all bits as live).
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Type *T = I.getType();
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if (T->isIntOrIntVectorTy()) {
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if (AliveBits.try_emplace(&I, T->getScalarSizeInBits(), 0).second)
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Worklist.insert(&I);
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continue;
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}
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// Non-integer-typed instructions...
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for (Use &OI : I.operands()) {
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if (Instruction *J = dyn_cast<Instruction>(OI)) {
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Type *T = J->getType();
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if (T->isIntOrIntVectorTy())
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AliveBits[J] = APInt::getAllOnesValue(T->getScalarSizeInBits());
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Worklist.insert(J);
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}
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}
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// To save memory, we don't add I to the Visited set here. Instead, we
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// check isAlwaysLive on every instruction when searching for dead
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// instructions later (we need to check isAlwaysLive for the
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// integer-typed instructions anyway).
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}
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// Propagate liveness backwards to operands.
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while (!Worklist.empty()) {
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Instruction *UserI = Worklist.pop_back_val();
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LLVM_DEBUG(dbgs() << "DemandedBits: Visiting: " << *UserI);
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APInt AOut;
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if (UserI->getType()->isIntOrIntVectorTy()) {
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AOut = AliveBits[UserI];
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LLVM_DEBUG(dbgs() << " Alive Out: 0x"
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<< Twine::utohexstr(AOut.getLimitedValue()));
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}
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LLVM_DEBUG(dbgs() << "\n");
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if (!UserI->getType()->isIntOrIntVectorTy())
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Visited.insert(UserI);
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KnownBits Known, Known2;
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bool KnownBitsComputed = false;
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// Compute the set of alive bits for each operand. These are anded into the
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// existing set, if any, and if that changes the set of alive bits, the
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// operand is added to the work-list.
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for (Use &OI : UserI->operands()) {
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// We also want to detect dead uses of arguments, but will only store
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// demanded bits for instructions.
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Instruction *I = dyn_cast<Instruction>(OI);
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if (!I && !isa<Argument>(OI))
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continue;
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Type *T = OI->getType();
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if (T->isIntOrIntVectorTy()) {
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unsigned BitWidth = T->getScalarSizeInBits();
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APInt AB = APInt::getAllOnesValue(BitWidth);
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if (UserI->getType()->isIntOrIntVectorTy() && !AOut &&
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!isAlwaysLive(UserI)) {
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// If all bits of the output are dead, then all bits of the input
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// are also dead.
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AB = APInt(BitWidth, 0);
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} else {
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// Bits of each operand that are used to compute alive bits of the
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// output are alive, all others are dead.
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determineLiveOperandBits(UserI, OI, OI.getOperandNo(), AOut, AB,
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Known, Known2, KnownBitsComputed);
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// Keep track of uses which have no demanded bits.
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if (AB.isNullValue())
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DeadUses.insert(&OI);
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else
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DeadUses.erase(&OI);
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}
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if (I) {
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// If we've added to the set of alive bits (or the operand has not
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// been previously visited), then re-queue the operand to be visited
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// again.
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APInt ABPrev(BitWidth, 0);
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auto ABI = AliveBits.find(I);
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if (ABI != AliveBits.end())
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ABPrev = ABI->second;
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APInt ABNew = AB | ABPrev;
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if (ABNew != ABPrev || ABI == AliveBits.end()) {
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AliveBits[I] = std::move(ABNew);
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Worklist.insert(I);
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}
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}
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} else if (I && !Visited.count(I)) {
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Worklist.insert(I);
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}
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}
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}
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}
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APInt DemandedBits::getDemandedBits(Instruction *I) {
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performAnalysis();
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auto Found = AliveBits.find(I);
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if (Found != AliveBits.end())
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return Found->second;
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const DataLayout &DL = I->getModule()->getDataLayout();
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return APInt::getAllOnesValue(
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DL.getTypeSizeInBits(I->getType()->getScalarType()));
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}
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bool DemandedBits::isInstructionDead(Instruction *I) {
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performAnalysis();
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return !Visited.count(I) && AliveBits.find(I) == AliveBits.end() &&
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!isAlwaysLive(I);
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}
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bool DemandedBits::isUseDead(Use *U) {
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// We only track integer uses, everything else is assumed live.
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if (!(*U)->getType()->isIntOrIntVectorTy())
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return false;
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// Uses by always-live instructions are never dead.
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Instruction *UserI = cast<Instruction>(U->getUser());
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if (isAlwaysLive(UserI))
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return false;
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performAnalysis();
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if (DeadUses.count(U))
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return true;
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// If no output bits are demanded, no input bits are demanded and the use
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// is dead. These uses might not be explicitly present in the DeadUses map.
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if (UserI->getType()->isIntOrIntVectorTy()) {
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auto Found = AliveBits.find(UserI);
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if (Found != AliveBits.end() && Found->second.isNullValue())
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return true;
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}
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return false;
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}
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void DemandedBits::print(raw_ostream &OS) {
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performAnalysis();
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for (auto &KV : AliveBits) {
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OS << "DemandedBits: 0x" << Twine::utohexstr(KV.second.getLimitedValue())
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<< " for " << *KV.first << '\n';
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}
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}
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FunctionPass *llvm::createDemandedBitsWrapperPass() {
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return new DemandedBitsWrapperPass();
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}
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AnalysisKey DemandedBitsAnalysis::Key;
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DemandedBits DemandedBitsAnalysis::run(Function &F,
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FunctionAnalysisManager &AM) {
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auto &AC = AM.getResult<AssumptionAnalysis>(F);
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auto &DT = AM.getResult<DominatorTreeAnalysis>(F);
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return DemandedBits(F, AC, DT);
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}
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PreservedAnalyses DemandedBitsPrinterPass::run(Function &F,
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FunctionAnalysisManager &AM) {
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AM.getResult<DemandedBitsAnalysis>(F).print(OS);
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return PreservedAnalyses::all();
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}
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