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1cc9a9a285
The current implementation of ThumbRegisterInfo::saveScavengerRegister is bad for two reasons: one, it's buggy, and two, it blocks using R12 for other optimizations. So this patch gets rid of it, and adds the necessary support for using an ordinary emergency spill slot on Thumb1. (Specifically, I think saveScavengerRegister was broken by r305625, and nobody noticed for two years because the codepath is almost never used. The new code will also probably not be used much, but it now has better tests, and if we fail to emit a necessary emergency spill slot we get a reasonable error message instead of a miscompile.) A rough outline of the changes in the patch: 1. Gets rid of ThumbRegisterInfo::saveScavengerRegister. 2. Modifies ARMFrameLowering::determineCalleeSaves to allocate an emergency spill slot for Thumb1. 3. Implements useFPForScavengingIndex, so the emergency spill slot isn't placed at a negative offset from FP on Thumb1. 4. Modifies the heuristics for allocating an emergency spill slot to support Thumb1. This includes fixing ExtraCSSpill so we don't try to use "lr" as a substitute for allocating an emergency spill slot. 5. Allocates a base pointer in more cases, so the emergency spill slot is always accessible. 6. Modifies ARMFrameLowering::ResolveFrameIndexReference to compute the right offset in the new cases where we're forcing a base pointer. 7. Ensures we never generate a load or store with an offset outside of its frame object. This makes the heuristics more straightforward. 8. Changes Thumb1 prologue and epilogue emission so it never uses register scavenging. Some of the changes to the emergency spill slot heuristics in determineCalleeSaves affect ARM/Thumb2; hopefully, they should allow the compiler to avoid allocating an emergency spill slot in cases where it isn't necessary. The rest of the changes should only affect Thumb1. Differential Revision: https://reviews.llvm.org/D63677 llvm-svn: 364490
116 lines
3.3 KiB
LLVM
116 lines
3.3 KiB
LLVM
; RUN: llc < %s -mtriple=thumb-apple-ios | FileCheck %s --check-prefix=CHECK --check-prefix=ALIGN4
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; RUN: llc < %s -mtriple=thumb-none-eabi | FileCheck %s --check-prefix=CHECK --check-prefix=ALIGN8
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; RUN: llc < %s -o %t -filetype=obj -mtriple=thumbv6-apple-ios
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; RUN: llvm-objdump -triple=thumbv6-apple-ios -d %t | FileCheck %s --check-prefix=CHECK --check-prefix=ALIGN4
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; RUN: llc < %s -o %t -filetype=obj -mtriple=thumbv6-none-eabi
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; RUN: llvm-objdump -triple=thumbv6-none-eabi -d %t | FileCheck %s --check-prefix=CHECK --check-prefix=ALIGN8
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; Largest stack for which a single tADDspi/tSUBspi is enough
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define void @test1() {
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; CHECK-LABEL: test1:
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; CHECK: sub sp, #508
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; CHECK: add sp, #508
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%tmp = alloca [ 508 x i8 ] , align 4
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ret void
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}
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; Largest stack for which three tADDspi/tSUBspis are enough
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define void @test100() {
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; CHECK-LABEL: test100:
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; CHECK: sub sp, #508
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; CHECK: sub sp, #508
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; CHECK: sub sp, #508
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; CHECK: add sp, #508
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; CHECK: add sp, #508
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; CHECK: add sp, #508
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%tmp = alloca [ 1524 x i8 ] , align 4
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ret void
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}
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; Largest stack for which three tADDspi/tSUBspis are enough
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define void @test100_nofpelim() "no-frame-pointer-elim"="true" {
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; CHECK-LABEL: test100_nofpelim:
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; CHECK: sub sp, #508
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; CHECK: sub sp, #508
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; CHECK: sub sp, #508
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; CHECK: subs r4, r7, #7
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; CHECK: subs r4, #1
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; CHECK: mov sp, r4
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%tmp = alloca [ 1524 x i8 ] , align 4
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ret void
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}
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; Smallest stack for which we use a constant pool
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define void @test2() {
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; CHECK-LABEL: test2:
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; CHECK: ldr [[TEMP:r[0-7]]],
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; CHECK: add sp, [[TEMP]]
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; CHECK: ldr [[TEMP:r[0-7]]],
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; CHECK: add sp, [[TEMP]]
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%tmp = alloca [ 1528 x i8 ] , align 4
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ret void
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}
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; Smallest stack for which we use a constant pool
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define void @test2_nofpelim() "no-frame-pointer-elim"="true" {
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; CHECK-LABEL: test2_nofpelim:
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; CHECK: ldr [[TEMP:r[0-7]]],
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; CHECK: add sp, [[TEMP]]
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; CHECK: subs r4, r7, #7
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; CHECK: subs r4, #1
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; CHECK: mov sp, r4
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%tmp = alloca [ 1528 x i8 ] , align 4
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ret void
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}
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define i32 @test3() {
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; CHECK-LABEL: test3:
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; CHECK: ldr [[TEMP:r[0-7]]],
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; CHECK: add sp, [[TEMP]]
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; CHECK: ldr [[TEMP2:r[0-7]]],
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; CHECK: add [[TEMP2]], sp
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; CHECK: ldr [[TEMP3:r[0-7]]],
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; CHECK: add sp, [[TEMP3]]
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%retval = alloca i32, align 4
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%tmp = alloca i32, align 4
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%a = alloca [805306369 x i8], align 4
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store i32 0, i32* %tmp
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%tmp1 = load i32, i32* %tmp
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ret i32 %tmp1
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}
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define i32 @test3_nofpelim() "no-frame-pointer-elim"="true" {
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; CHECK-LABEL: test3_nofpelim:
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; CHECK: ldr [[TEMP:r[0-7]]],
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; CHECK: add sp, [[TEMP]]
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; CHECK: ldr [[TEMP2:r[0-7]]],
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; CHECK: add [[TEMP2]], sp
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; CHECK: subs r4, r7,
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; CHECK: mov sp, r4
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%retval = alloca i32, align 4
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%tmp = alloca i32, align 4
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%a = alloca [805306369 x i8], align 8
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store i32 0, i32* %tmp
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%tmp1 = load i32, i32* %tmp
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ret i32 %tmp1
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}
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; Here, the adds get optimized out because they are dead, but the calculation
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; of the address of stack_a is dead but not optimized out. When the address
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; calculation gets expanded to two instructions, we need to avoid reading a
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; dead register.
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; No CHECK lines (just test for crashes), as we hope this will be optimised
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; better in future.
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define i32 @test4() {
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entry:
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%stack_a = alloca i8, align 1
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%stack_b = alloca [256 x i32*], align 4
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%int = ptrtoint i8* %stack_a to i32
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%add = add i32 %int, 1
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br label %block2
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block2:
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%add2 = add i32 %add, 1
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ret i32 0
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}
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