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to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
207 lines
5.8 KiB
C++
207 lines
5.8 KiB
C++
//===- MipsABIFlagsSection.h - Mips ELF ABI Flags Section -------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSABIFLAGSSECTION_H
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#define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSABIFLAGSSECTION_H
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#include "llvm/ADT/StringRef.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/MipsABIFlags.h"
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#include <cstdint>
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namespace llvm {
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class MCStreamer;
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struct MipsABIFlagsSection {
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// Internal representation of the fp_abi related values used in .module.
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enum class FpABIKind { ANY, XX, S32, S64, SOFT };
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// Version of flags structure.
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uint16_t Version = 0;
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// The level of the ISA: 1-5, 32, 64.
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uint8_t ISALevel = 0;
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// The revision of ISA: 0 for MIPS V and below, 1-n otherwise.
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uint8_t ISARevision = 0;
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// The size of general purpose registers.
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Mips::AFL_REG GPRSize = Mips::AFL_REG_NONE;
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// The size of co-processor 1 registers.
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Mips::AFL_REG CPR1Size = Mips::AFL_REG_NONE;
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// The size of co-processor 2 registers.
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Mips::AFL_REG CPR2Size = Mips::AFL_REG_NONE;
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// Processor-specific extension.
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Mips::AFL_EXT ISAExtension = Mips::AFL_EXT_NONE;
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// Mask of ASEs used.
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uint32_t ASESet = 0;
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bool OddSPReg = false;
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bool Is32BitABI = false;
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protected:
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// The floating-point ABI.
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FpABIKind FpABI = FpABIKind::ANY;
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public:
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MipsABIFlagsSection() = default;
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uint16_t getVersionValue() { return (uint16_t)Version; }
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uint8_t getISALevelValue() { return (uint8_t)ISALevel; }
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uint8_t getISARevisionValue() { return (uint8_t)ISARevision; }
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uint8_t getGPRSizeValue() { return (uint8_t)GPRSize; }
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uint8_t getCPR1SizeValue();
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uint8_t getCPR2SizeValue() { return (uint8_t)CPR2Size; }
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uint8_t getFpABIValue();
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uint32_t getISAExtensionValue() { return (uint32_t)ISAExtension; }
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uint32_t getASESetValue() { return (uint32_t)ASESet; }
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uint32_t getFlags1Value() {
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uint32_t Value = 0;
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if (OddSPReg)
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Value |= (uint32_t)Mips::AFL_FLAGS1_ODDSPREG;
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return Value;
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}
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uint32_t getFlags2Value() { return 0; }
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FpABIKind getFpABI() { return FpABI; }
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void setFpABI(FpABIKind Value, bool IsABI32Bit) {
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FpABI = Value;
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Is32BitABI = IsABI32Bit;
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}
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StringRef getFpABIString(FpABIKind Value);
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template <class PredicateLibrary>
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void setISALevelAndRevisionFromPredicates(const PredicateLibrary &P) {
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if (P.hasMips64()) {
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ISALevel = 64;
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if (P.hasMips64r6())
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ISARevision = 6;
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else if (P.hasMips64r5())
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ISARevision = 5;
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else if (P.hasMips64r3())
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ISARevision = 3;
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else if (P.hasMips64r2())
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ISARevision = 2;
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else
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ISARevision = 1;
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} else if (P.hasMips32()) {
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ISALevel = 32;
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if (P.hasMips32r6())
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ISARevision = 6;
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else if (P.hasMips32r5())
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ISARevision = 5;
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else if (P.hasMips32r3())
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ISARevision = 3;
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else if (P.hasMips32r2())
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ISARevision = 2;
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else
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ISARevision = 1;
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} else {
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ISARevision = 0;
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if (P.hasMips5())
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ISALevel = 5;
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else if (P.hasMips4())
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ISALevel = 4;
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else if (P.hasMips3())
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ISALevel = 3;
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else if (P.hasMips2())
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ISALevel = 2;
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else if (P.hasMips1())
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ISALevel = 1;
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else
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llvm_unreachable("Unknown ISA level!");
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}
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}
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template <class PredicateLibrary>
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void setGPRSizeFromPredicates(const PredicateLibrary &P) {
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GPRSize = P.isGP64bit() ? Mips::AFL_REG_64 : Mips::AFL_REG_32;
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}
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template <class PredicateLibrary>
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void setCPR1SizeFromPredicates(const PredicateLibrary &P) {
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if (P.useSoftFloat())
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CPR1Size = Mips::AFL_REG_NONE;
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else if (P.hasMSA())
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CPR1Size = Mips::AFL_REG_128;
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else
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CPR1Size = P.isFP64bit() ? Mips::AFL_REG_64 : Mips::AFL_REG_32;
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}
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template <class PredicateLibrary>
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void setISAExtensionFromPredicates(const PredicateLibrary &P) {
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if (P.hasCnMips())
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ISAExtension = Mips::AFL_EXT_OCTEON;
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else
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ISAExtension = Mips::AFL_EXT_NONE;
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}
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template <class PredicateLibrary>
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void setASESetFromPredicates(const PredicateLibrary &P) {
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ASESet = 0;
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if (P.hasDSP())
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ASESet |= Mips::AFL_ASE_DSP;
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if (P.hasDSPR2())
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ASESet |= Mips::AFL_ASE_DSPR2;
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if (P.hasMSA())
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ASESet |= Mips::AFL_ASE_MSA;
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if (P.inMicroMipsMode())
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ASESet |= Mips::AFL_ASE_MICROMIPS;
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if (P.inMips16Mode())
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ASESet |= Mips::AFL_ASE_MIPS16;
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if (P.hasMT())
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ASESet |= Mips::AFL_ASE_MT;
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if (P.hasCRC())
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ASESet |= Mips::AFL_ASE_CRC;
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if (P.hasVirt())
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ASESet |= Mips::AFL_ASE_VIRT;
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if (P.hasGINV())
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ASESet |= Mips::AFL_ASE_GINV;
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}
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template <class PredicateLibrary>
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void setFpAbiFromPredicates(const PredicateLibrary &P) {
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Is32BitABI = P.isABI_O32();
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FpABI = FpABIKind::ANY;
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if (P.useSoftFloat())
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FpABI = FpABIKind::SOFT;
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else if (P.isABI_N32() || P.isABI_N64())
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FpABI = FpABIKind::S64;
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else if (P.isABI_O32()) {
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if (P.isABI_FPXX())
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FpABI = FpABIKind::XX;
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else if (P.isFP64bit())
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FpABI = FpABIKind::S64;
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else
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FpABI = FpABIKind::S32;
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}
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}
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template <class PredicateLibrary>
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void setAllFromPredicates(const PredicateLibrary &P) {
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setISALevelAndRevisionFromPredicates(P);
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setGPRSizeFromPredicates(P);
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setCPR1SizeFromPredicates(P);
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setISAExtensionFromPredicates(P);
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setASESetFromPredicates(P);
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setFpAbiFromPredicates(P);
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OddSPReg = P.useOddSPReg();
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}
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};
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MCStreamer &operator<<(MCStreamer &OS, MipsABIFlagsSection &ABIFlagsSection);
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSABIFLAGSSECTION_H
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