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614 lines
15 KiB
TableGen
614 lines
15 KiB
TableGen
//=- Mips32r6InstrFormats.td - Mips32r6 Instruction Formats -*- tablegen -*-==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes Mips32r6 instruction formats.
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//
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//===----------------------------------------------------------------------===//
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class R6MMR6Rel;
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def MipsR62MicroMipsR6 : InstrMapping {
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let FilterClass = "R6MMR6Rel";
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// Instructions with the same BaseOpcode and isNVStore values form a row.
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let RowFields = ["BaseOpcode"];
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// Instructions with the same predicate sense form a column.
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let ColFields = ["Arch"];
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// The key column is the unpredicated instructions.
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let KeyCol = ["mipsr6"];
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// Value columns are PredSense=true and PredSense=false
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let ValueCols = [["mipsr6"], ["micromipsr6"]];
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}
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class MipsR6Arch<string opstr> {
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string Arch = "mipsr6";
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string BaseOpcode = opstr;
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}
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class MipsR6Inst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
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let DecoderNamespace = "Mips32r6_64r6";
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let EncodingPredicates = [HasStdEnc];
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}
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//===----------------------------------------------------------------------===//
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//
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// Field Values
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//
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//===----------------------------------------------------------------------===//
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class OPGROUP<bits<6> Val> {
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bits<6> Value = Val;
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}
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def OPGROUP_COP0 : OPGROUP<0b010000>;
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def OPGROUP_COP1 : OPGROUP<0b010001>;
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def OPGROUP_COP2 : OPGROUP<0b010010>;
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def OPGROUP_ADDI : OPGROUP<0b001000>;
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def OPGROUP_AUI : OPGROUP<0b001111>;
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def OPGROUP_BLEZ : OPGROUP<0b000110>;
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def OPGROUP_BGTZ : OPGROUP<0b000111>;
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def OPGROUP_BLEZL : OPGROUP<0b010110>;
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def OPGROUP_BGTZL : OPGROUP<0b010111>;
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def OPGROUP_DADDI : OPGROUP<0b011000>;
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def OPGROUP_DAUI : OPGROUP<0b011101>;
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def OPGROUP_PCREL : OPGROUP<0b111011>;
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def OPGROUP_REGIMM : OPGROUP<0b000001>;
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def OPGROUP_SPECIAL : OPGROUP<0b000000>;
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// The spec occasionally names this value LL, LLD, SC, or SCD.
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def OPGROUP_SPECIAL3 : OPGROUP<0b011111>;
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// The spec names this constant LWC2, LDC2, SWC2, and SDC2 in different places.
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def OPGROUP_COP2LDST : OPGROUP<0b010010>;
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class OPCODE2<bits<2> Val> {
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bits<2> Value = Val;
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}
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def OPCODE2_ADDIUPC : OPCODE2<0b00>;
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def OPCODE2_LWPC : OPCODE2<0b01>;
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def OPCODE2_LWUPC : OPCODE2<0b10>;
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class OPCODE3<bits<3> Val> {
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bits<3> Value = Val;
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}
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def OPCODE3_LDPC : OPCODE3<0b110>;
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class OPCODE5<bits<5> Val> {
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bits<5> Value = Val;
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}
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def OPCODE5_ALUIPC : OPCODE5<0b11111>;
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def OPCODE5_AUIPC : OPCODE5<0b11110>;
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def OPCODE5_DAHI : OPCODE5<0b00110>;
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def OPCODE5_DATI : OPCODE5<0b11110>;
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def OPCODE5_BC1EQZ : OPCODE5<0b01001>;
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def OPCODE5_BC1NEZ : OPCODE5<0b01101>;
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def OPCODE5_BC2EQZ : OPCODE5<0b01001>;
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def OPCODE5_BC2NEZ : OPCODE5<0b01101>;
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def OPCODE5_BGEZAL : OPCODE5<0b10001>;
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def OPCODE5_SIGRIE : OPCODE5<0b10111>;
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// The next four constants are unnamed in the spec. These names are taken from
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// the OPGROUP names they are used with.
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def OPCODE5_LDC2 : OPCODE5<0b01110>;
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def OPCODE5_LWC2 : OPCODE5<0b01010>;
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def OPCODE5_SDC2 : OPCODE5<0b01111>;
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def OPCODE5_SWC2 : OPCODE5<0b01011>;
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class OPCODE6<bits<6> Val> {
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bits<6> Value = Val;
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}
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def OPCODE6_ALIGN : OPCODE6<0b100000>;
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def OPCODE6_DALIGN : OPCODE6<0b100100>;
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def OPCODE6_BITSWAP : OPCODE6<0b100000>;
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def OPCODE6_DBITSWAP : OPCODE6<0b100100>;
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def OPCODE6_JALR : OPCODE6<0b001001>;
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def OPCODE6_CACHE : OPCODE6<0b100101>;
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def OPCODE6_PREF : OPCODE6<0b110101>;
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// The next four constants are unnamed in the spec. These names are taken from
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// the OPGROUP names they are used with.
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def OPCODE6_LL : OPCODE6<0b110110>;
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def OPCODE6_LLD : OPCODE6<0b110111>;
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def OPCODE6_SC : OPCODE6<0b100110>;
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def OPCODE6_SCD : OPCODE6<0b100111>;
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def OPCODE6_CLO : OPCODE6<0b010001>;
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def OPCODE6_CLZ : OPCODE6<0b010000>;
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def OPCODE6_DCLO : OPCODE6<0b010011>;
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def OPCODE6_DCLZ : OPCODE6<0b010010>;
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def OPCODE6_LSA : OPCODE6<0b000101>;
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def OPCODE6_DLSA : OPCODE6<0b010101>;
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def OPCODE6_SDBBP : OPCODE6<0b001110>;
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class FIELD_FMT<bits<5> Val> {
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bits<5> Value = Val;
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}
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def FIELD_FMT_S : FIELD_FMT<0b10000>;
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def FIELD_FMT_D : FIELD_FMT<0b10001>;
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class FIELD_CMP_COND<bits<5> Val> {
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bits<5> Value = Val;
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}
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// Note: The CMP_COND_FMT names differ from the C_COND_FMT names.
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def FIELD_CMP_COND_AF : FIELD_CMP_COND<0b00000>;
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def FIELD_CMP_COND_UN : FIELD_CMP_COND<0b00001>;
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def FIELD_CMP_COND_EQ : FIELD_CMP_COND<0b00010>;
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def FIELD_CMP_COND_UEQ : FIELD_CMP_COND<0b00011>;
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def FIELD_CMP_COND_LT : FIELD_CMP_COND<0b00100>;
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def FIELD_CMP_COND_ULT : FIELD_CMP_COND<0b00101>;
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def FIELD_CMP_COND_LE : FIELD_CMP_COND<0b00110>;
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def FIELD_CMP_COND_ULE : FIELD_CMP_COND<0b00111>;
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def FIELD_CMP_COND_SAF : FIELD_CMP_COND<0b01000>;
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def FIELD_CMP_COND_SUN : FIELD_CMP_COND<0b01001>;
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def FIELD_CMP_COND_SEQ : FIELD_CMP_COND<0b01010>;
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def FIELD_CMP_COND_SUEQ : FIELD_CMP_COND<0b01011>;
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def FIELD_CMP_COND_SLT : FIELD_CMP_COND<0b01100>;
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def FIELD_CMP_COND_SULT : FIELD_CMP_COND<0b01101>;
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def FIELD_CMP_COND_SLE : FIELD_CMP_COND<0b01110>;
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def FIELD_CMP_COND_SULE : FIELD_CMP_COND<0b01111>;
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class FIELD_CMP_FORMAT<bits<5> Val> {
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bits<5> Value = Val;
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}
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def FIELD_CMP_FORMAT_S : FIELD_CMP_FORMAT<0b10100>;
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def FIELD_CMP_FORMAT_D : FIELD_CMP_FORMAT<0b10101>;
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//===----------------------------------------------------------------------===//
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//
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// Disambiguators
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//
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//===----------------------------------------------------------------------===//
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//
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// Some encodings are ambiguous except by comparing field values.
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class DecodeDisambiguates<string Name> {
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string DecoderMethod = !strconcat("Decode", Name);
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}
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class DecodeDisambiguatedBy<string Name> : DecodeDisambiguates<Name> {
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string DecoderNamespace = "Mips32r6_64r6_Ambiguous";
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}
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//===----------------------------------------------------------------------===//
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//
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// Encoding Formats
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//
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//===----------------------------------------------------------------------===//
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class AUI_FM : MipsR6Inst {
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bits<5> rs;
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bits<5> rt;
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bits<16> imm;
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bits<32> Inst;
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let Inst{31-26} = OPGROUP_AUI.Value;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-0} = imm;
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}
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class DAUI_FM : AUI_FM {
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let Inst{31-26} = OPGROUP_DAUI.Value;
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}
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class BAL_FM : MipsR6Inst {
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bits<16> offset;
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bits<32> Inst;
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let Inst{31-26} = OPGROUP_REGIMM.Value;
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let Inst{25-21} = 0b00000;
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let Inst{20-16} = OPCODE5_BGEZAL.Value;
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let Inst{15-0} = offset;
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}
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class COP0_EVP_DVP_FM<bits<1> sc> : MipsR6Inst {
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bits<5> rt;
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bits<32> Inst;
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let Inst{31-26} = OPGROUP_COP0.Value;
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let Inst{25-21} = 0b01011;
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let Inst{20-16} = rt;
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let Inst{15-11} = 0b00000;
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let Inst{10-6} = 0b00000;
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let Inst{5} = sc;
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let Inst{4-3} = 0b00;
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let Inst{2-0} = 0b100;
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}
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class COP1_2R_FM<bits<6> funct, FIELD_FMT Format> : MipsR6Inst {
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bits<5> fs;
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bits<5> fd;
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bits<32> Inst;
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let Inst{31-26} = OPGROUP_COP1.Value;
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let Inst{25-21} = Format.Value;
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let Inst{20-16} = 0b00000;
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let Inst{15-11} = fs;
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let Inst{10-6} = fd;
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let Inst{5-0} = funct;
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}
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class COP1_3R_FM<bits<6> funct, FIELD_FMT Format> : MipsR6Inst {
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bits<5> ft;
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bits<5> fs;
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bits<5> fd;
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bits<32> Inst;
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let Inst{31-26} = OPGROUP_COP1.Value;
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let Inst{25-21} = Format.Value;
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let Inst{20-16} = ft;
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let Inst{15-11} = fs;
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let Inst{10-6} = fd;
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let Inst{5-0} = funct;
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}
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class COP1_BCCZ_FM<OPCODE5 Operation> : MipsR6Inst {
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bits<5> ft;
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bits<16> offset;
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bits<32> Inst;
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let Inst{31-26} = OPGROUP_COP1.Value;
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let Inst{25-21} = Operation.Value;
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let Inst{20-16} = ft;
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let Inst{15-0} = offset;
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}
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class COP2_BCCZ_FM<OPCODE5 Operation> : MipsR6Inst {
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bits<5> ct;
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bits<16> offset;
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bits<32> Inst;
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let Inst{31-26} = OPGROUP_COP2.Value;
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let Inst{25-21} = Operation.Value;
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let Inst{20-16} = ct;
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let Inst{15-0} = offset;
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}
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class PCREL16_FM<OPCODE5 Operation> : MipsR6Inst {
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bits<5> rs;
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bits<16> imm;
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bits<32> Inst;
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let Inst{31-26} = OPGROUP_PCREL.Value;
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let Inst{25-21} = rs;
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let Inst{20-16} = Operation.Value;
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let Inst{15-0} = imm;
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}
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class PCREL19_FM<OPCODE2 Operation> : MipsR6Inst {
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bits<5> rs;
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bits<19> imm;
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bits<32> Inst;
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let Inst{31-26} = OPGROUP_PCREL.Value;
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let Inst{25-21} = rs;
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let Inst{20-19} = Operation.Value;
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let Inst{18-0} = imm;
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}
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class PCREL18_FM<OPCODE3 Operation> : MipsR6Inst {
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bits<5> rs;
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bits<18> imm;
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bits<32> Inst;
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let Inst{31-26} = OPGROUP_PCREL.Value;
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let Inst{25-21} = rs;
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let Inst{20-18} = Operation.Value;
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let Inst{17-0} = imm;
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}
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class SPECIAL3_2R_FM<OPCODE6 Operation> : MipsR6Inst {
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bits<5> rd;
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bits<5> rt;
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bits<32> Inst;
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let Inst{31-26} = OPGROUP_SPECIAL3.Value;
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let Inst{25-21} = 0b00000;
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let Inst{20-16} = rt;
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let Inst{15-11} = rd;
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let Inst{10-6} = 0b00000;
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let Inst{5-0} = Operation.Value;
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}
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class SPECIAL3_MEM_FM<OPCODE6 Operation> : MipsR6Inst {
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bits<21> addr;
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bits<5> hint;
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bits<5> base = addr{20-16};
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bits<9> offset = addr{8-0};
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bits<32> Inst;
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let Inst{31-26} = OPGROUP_SPECIAL3.Value;
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let Inst{25-21} = base;
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let Inst{20-16} = hint;
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let Inst{15-7} = offset;
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let Inst{6} = 0;
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let Inst{5-0} = Operation.Value;
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}
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class SPECIAL_2R_FM<OPCODE6 Operation> : MipsR6Inst {
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bits<5> rd;
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bits<5> rs;
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bits<32> Inst;
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let Inst{31-26} = OPGROUP_SPECIAL.Value;
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let Inst{25-21} = rs;
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let Inst{20-16} = 0b00000;
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let Inst{15-11} = rd;
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let Inst{10-6} = 0b00001;
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let Inst{5-0} = Operation.Value;
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}
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class SPECIAL_3R_FM<bits<5> mulop, bits<6> funct> : MipsR6Inst {
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bits<5> rd;
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bits<5> rs;
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bits<5> rt;
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bits<32> Inst;
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let Inst{31-26} = OPGROUP_SPECIAL.Value;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-11} = rd;
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let Inst{10-6} = mulop;
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let Inst{5-0} = funct;
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}
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class SPECIAL_SDBBP_FM : MipsR6Inst {
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bits<20> code_;
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bits<32> Inst;
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let Inst{31-26} = OPGROUP_SPECIAL.Value;
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let Inst{25-6} = code_;
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let Inst{5-0} = OPCODE6_SDBBP.Value;
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}
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// This class is ambiguous with other branches:
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// BEQC/BNEC require that rs < rt && rs != 0
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class CMP_BRANCH_2R_OFF16_FM<OPGROUP funct> : MipsR6Inst {
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bits<5> rs;
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bits<5> rt;
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bits<16> offset;
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bits<32> Inst;
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let Inst{31-26} = funct.Value;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-0} = offset;
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}
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// This class is ambiguous with other branches:
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// BLEZC/BGEZC/BEQZALC/BNEZALC/BGTZALC require that rs == 0 && rt != 0
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// The '1R_RT' in the name means 1 register in the rt field.
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class CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP funct> : MipsR6Inst {
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bits<5> rt;
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bits<16> offset;
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bits<32> Inst;
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let Inst{31-26} = funct.Value;
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let Inst{25-21} = 0b00000;
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let Inst{20-16} = rt;
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let Inst{15-0} = offset;
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}
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// This class is ambiguous with other branches:
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// BLTZC/BGTZC/BLTZALC/BGEZALC require that rs == rt && rt != 0
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// The '1R_BOTH' in the name means 1 register in both the rs and rt fields.
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class CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP funct> : MipsR6Inst {
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bits<5> rt;
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bits<16> offset;
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bits<32> Inst;
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let Inst{31-26} = funct.Value;
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let Inst{25-21} = rt;
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let Inst{20-16} = rt;
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let Inst{15-0} = offset;
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}
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class CMP_BRANCH_OFF21_FM<bits<6> funct> : MipsR6Inst {
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bits<5> rs; // rs != 0
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bits<21> offset;
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bits<32> Inst;
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let Inst{31-26} = funct;
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let Inst{25-21} = rs;
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let Inst{20-0} = offset;
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}
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class JMP_IDX_COMPACT_FM<bits<6> funct> : MipsR6Inst {
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bits<5> rt;
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bits<16> offset;
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bits<32> Inst;
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let Inst{31-26} = funct;
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let Inst{25-21} = 0b00000;
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let Inst{20-16} = rt;
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let Inst{15-0} = offset;
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}
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class BRANCH_OFF26_FM<bits<6> funct> : MipsR6Inst {
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bits<32> Inst;
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bits<26> offset;
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let Inst{31-26} = funct;
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let Inst{25-0} = offset;
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}
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class SPECIAL3_ALIGN_FM<OPCODE6 Operation> : MipsR6Inst {
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bits<5> rd;
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bits<5> rs;
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bits<5> rt;
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bits<2> bp;
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bits<32> Inst;
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let Inst{31-26} = OPGROUP_SPECIAL3.Value;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-11} = rd;
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let Inst{10-8} = 0b010;
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let Inst{7-6} = bp;
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let Inst{5-0} = Operation.Value;
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}
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class SPECIAL3_DALIGN_FM<OPCODE6 Operation> : MipsR6Inst {
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bits<5> rd;
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bits<5> rs;
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bits<5> rt;
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bits<3> bp;
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bits<32> Inst;
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let Inst{31-26} = OPGROUP_SPECIAL3.Value;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-11} = rd;
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let Inst{10-9} = 0b01;
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let Inst{8-6} = bp;
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let Inst{5-0} = Operation.Value;
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}
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class SPECIAL3_LL_SC_FM<OPCODE6 Operation> : MipsR6Inst {
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bits<5> rt;
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bits<21> addr;
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bits<5> base = addr{20-16};
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bits<9> offset = addr{8-0};
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bits<32> Inst;
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let Inst{31-26} = OPGROUP_SPECIAL3.Value;
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let Inst{25-21} = base;
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let Inst{20-16} = rt;
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let Inst{15-7} = offset;
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let Inst{5-0} = Operation.Value;
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string DecoderMethod = "DecodeSpecial3LlSc";
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}
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class SPECIAL_LSA_FM<OPCODE6 Operation> : MipsR6Inst {
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bits<5> rd;
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bits<5> rs;
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bits<5> rt;
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bits<2> imm2;
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bits<32> Inst;
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let Inst{31-26} = OPGROUP_SPECIAL.Value;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-11} = rd;
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let Inst{10-8} = 0b000;
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let Inst{7-6} = imm2;
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let Inst{5-0} = Operation.Value;
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}
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class REGIMM_FM<OPCODE5 Operation> : MipsR6Inst {
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bits<5> rs;
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bits<16> imm;
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bits<32> Inst;
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let Inst{31-26} = OPGROUP_REGIMM.Value;
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let Inst{25-21} = rs;
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let Inst{20-16} = Operation.Value;
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let Inst{15-0} = imm;
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}
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class COP1_CMP_CONDN_FM<FIELD_CMP_FORMAT Format,
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FIELD_CMP_COND Cond> : MipsR6Inst {
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bits<5> fd;
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bits<5> fs;
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bits<5> ft;
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bits<32> Inst;
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let Inst{31-26} = OPGROUP_COP1.Value;
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let Inst{25-21} = Format.Value;
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let Inst{20-16} = ft;
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let Inst{15-11} = fs;
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let Inst{10-6} = fd;
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let Inst{5} = 0;
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let Inst{4-0} = Cond.Value;
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}
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class JR_HB_R6_FM<OPCODE6 Operation> : MipsR6Inst {
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bits<5> rs;
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bits<32> Inst;
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let Inst{31-26} = OPGROUP_SPECIAL.Value;
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let Inst{25-21} = rs;
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let Inst{20-16} = 0;
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let Inst{15-11} = 0;
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let Inst{10} = 1;
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let Inst{9-6} = 0;
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let Inst{5-0} = Operation.Value;
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}
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class COP2LDST_FM<OPCODE5 Operation> : MipsR6Inst {
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bits<5> rt;
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bits<21> addr;
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bits<5> base = addr{20-16};
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bits<11> offset = addr{10-0};
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bits<32> Inst;
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let Inst{31-26} = OPGROUP_COP2LDST.Value;
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let Inst{25-21} = Operation.Value;
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let Inst{20-16} = rt;
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let Inst{15-11} = base;
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let Inst{10-0} = offset;
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}
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class SPECIAL3_2R_SZ_CRC<bits<2> sz, bits<3> direction> : MipsR6Inst {
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bits<5> rs;
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bits<5> rt;
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let Inst{31-26} = OPGROUP_SPECIAL3.Value;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-11} = 0b00000;
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let Inst{10-8} = direction;
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let Inst{7-6} = sz;
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let Inst{5-0} = 0b001111;
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string DecoderMethod = "DecodeCRC";
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}
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class SPECIAL3_GINV<bits<2> ginv> : MipsR6Inst {
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bits<5> rs;
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bits<2> type_;
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let Inst{31-26} = OPGROUP_SPECIAL3.Value;
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let Inst{25-21} = rs;
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let Inst{20-10} = 0x0;
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let Inst{9-8} = type_;
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let Inst{7-6} = ginv;
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let Inst{5-0} = 0b111101;
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}
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class SIGRIE_FM : MipsR6Inst {
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bits<16> code_;
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let Inst{31-26} = OPGROUP_REGIMM.Value;
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let Inst{25-21} = 0;
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let Inst{20-16} = OPCODE5_SIGRIE.Value;
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let Inst{15-0} = code_;
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}
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