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702 lines
23 KiB
C++
702 lines
23 KiB
C++
//===-- MipsExpandPseudoInsts.cpp - Expand pseudo instructions ------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a pass that expands pseudo instructions into target
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// instructions to allow proper scheduling, if-conversion, and other late
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// optimizations. This pass should be run after register allocation but before
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// the post-regalloc scheduling pass.
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//
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// This is currently only used for expanding atomic pseudos after register
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// allocation. We do this to avoid the fast register allocator introducing
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// spills between ll and sc. These stores cause some MIPS implementations to
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// abort the atomic RMW sequence.
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//
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//===----------------------------------------------------------------------===//
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#include "Mips.h"
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#include "MipsInstrInfo.h"
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#include "MipsSubtarget.h"
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#include "llvm/CodeGen/LivePhysRegs.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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using namespace llvm;
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#define DEBUG_TYPE "mips-pseudo"
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namespace {
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class MipsExpandPseudo : public MachineFunctionPass {
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public:
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static char ID;
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MipsExpandPseudo() : MachineFunctionPass(ID) {}
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const MipsInstrInfo *TII;
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const MipsSubtarget *STI;
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bool runOnMachineFunction(MachineFunction &Fn) override;
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MachineFunctionProperties getRequiredProperties() const override {
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return MachineFunctionProperties().set(
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MachineFunctionProperties::Property::NoVRegs);
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}
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StringRef getPassName() const override {
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return "Mips pseudo instruction expansion pass";
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}
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private:
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bool expandAtomicCmpSwap(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI);
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bool expandAtomicCmpSwapSubword(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI);
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bool expandAtomicBinOp(MachineBasicBlock &BB,
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MachineBasicBlock::iterator I,
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MachineBasicBlock::iterator &NMBBI, unsigned Size);
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bool expandAtomicBinOpSubword(MachineBasicBlock &BB,
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MachineBasicBlock::iterator I,
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MachineBasicBlock::iterator &NMBBI);
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bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NMBB);
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bool expandMBB(MachineBasicBlock &MBB);
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};
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char MipsExpandPseudo::ID = 0;
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}
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bool MipsExpandPseudo::expandAtomicCmpSwapSubword(
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MachineBasicBlock &BB, MachineBasicBlock::iterator I,
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MachineBasicBlock::iterator &NMBBI) {
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MachineFunction *MF = BB.getParent();
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const bool ArePtrs64bit = STI->getABI().ArePtrs64bit();
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DebugLoc DL = I->getDebugLoc();
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unsigned LL, SC;
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unsigned ZERO = Mips::ZERO;
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unsigned BNE = Mips::BNE;
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unsigned BEQ = Mips::BEQ;
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unsigned SEOp =
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I->getOpcode() == Mips::ATOMIC_CMP_SWAP_I8_POSTRA ? Mips::SEB : Mips::SEH;
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if (STI->inMicroMipsMode()) {
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LL = STI->hasMips32r6() ? Mips::LL_MMR6 : Mips::LL_MM;
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SC = STI->hasMips32r6() ? Mips::SC_MMR6 : Mips::SC_MM;
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BNE = STI->hasMips32r6() ? Mips::BNEC_MMR6 : Mips::BNE_MM;
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BEQ = STI->hasMips32r6() ? Mips::BEQC_MMR6 : Mips::BEQ_MM;
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} else {
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LL = STI->hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6)
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: (ArePtrs64bit ? Mips::LL64 : Mips::LL);
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SC = STI->hasMips32r6() ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6)
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: (ArePtrs64bit ? Mips::SC64 : Mips::SC);
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}
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unsigned Dest = I->getOperand(0).getReg();
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unsigned Ptr = I->getOperand(1).getReg();
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unsigned Mask = I->getOperand(2).getReg();
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unsigned ShiftCmpVal = I->getOperand(3).getReg();
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unsigned Mask2 = I->getOperand(4).getReg();
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unsigned ShiftNewVal = I->getOperand(5).getReg();
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unsigned ShiftAmnt = I->getOperand(6).getReg();
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unsigned Scratch = I->getOperand(7).getReg();
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unsigned Scratch2 = I->getOperand(8).getReg();
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// insert new blocks after the current block
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const BasicBlock *LLVM_BB = BB.getBasicBlock();
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MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
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MachineFunction::iterator It = ++BB.getIterator();
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MF->insert(It, loop1MBB);
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MF->insert(It, loop2MBB);
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MF->insert(It, sinkMBB);
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MF->insert(It, exitMBB);
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// Transfer the remainder of BB and its successor edges to exitMBB.
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exitMBB->splice(exitMBB->begin(), &BB,
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std::next(MachineBasicBlock::iterator(I)), BB.end());
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exitMBB->transferSuccessorsAndUpdatePHIs(&BB);
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// thisMBB:
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// ...
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// fallthrough --> loop1MBB
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BB.addSuccessor(loop1MBB, BranchProbability::getOne());
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loop1MBB->addSuccessor(sinkMBB);
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loop1MBB->addSuccessor(loop2MBB);
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loop1MBB->normalizeSuccProbs();
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loop2MBB->addSuccessor(loop1MBB);
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loop2MBB->addSuccessor(sinkMBB);
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loop2MBB->normalizeSuccProbs();
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sinkMBB->addSuccessor(exitMBB, BranchProbability::getOne());
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// loop1MBB:
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// ll dest, 0(ptr)
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// and Mask', dest, Mask
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// bne Mask', ShiftCmpVal, exitMBB
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BuildMI(loop1MBB, DL, TII->get(LL), Scratch).addReg(Ptr).addImm(0);
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BuildMI(loop1MBB, DL, TII->get(Mips::AND), Scratch2)
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.addReg(Scratch)
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.addReg(Mask);
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BuildMI(loop1MBB, DL, TII->get(BNE))
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.addReg(Scratch2).addReg(ShiftCmpVal).addMBB(sinkMBB);
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// loop2MBB:
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// and dest, dest, mask2
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// or dest, dest, ShiftNewVal
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// sc dest, dest, 0(ptr)
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// beq dest, $0, loop1MBB
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BuildMI(loop2MBB, DL, TII->get(Mips::AND), Scratch)
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.addReg(Scratch, RegState::Kill)
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.addReg(Mask2);
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BuildMI(loop2MBB, DL, TII->get(Mips::OR), Scratch)
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.addReg(Scratch, RegState::Kill)
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.addReg(ShiftNewVal);
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BuildMI(loop2MBB, DL, TII->get(SC), Scratch)
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.addReg(Scratch, RegState::Kill)
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.addReg(Ptr)
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.addImm(0);
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BuildMI(loop2MBB, DL, TII->get(BEQ))
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.addReg(Scratch, RegState::Kill)
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.addReg(ZERO)
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.addMBB(loop1MBB);
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// sinkMBB:
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// srl srlres, Mask', shiftamt
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// sign_extend dest,srlres
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BuildMI(sinkMBB, DL, TII->get(Mips::SRLV), Dest)
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.addReg(Scratch2)
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.addReg(ShiftAmnt);
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if (STI->hasMips32r2()) {
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BuildMI(sinkMBB, DL, TII->get(SEOp), Dest).addReg(Dest);
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} else {
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const unsigned ShiftImm =
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I->getOpcode() == Mips::ATOMIC_CMP_SWAP_I16_POSTRA ? 16 : 24;
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BuildMI(sinkMBB, DL, TII->get(Mips::SLL), Dest)
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.addReg(Dest, RegState::Kill)
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.addImm(ShiftImm);
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BuildMI(sinkMBB, DL, TII->get(Mips::SRA), Dest)
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.addReg(Dest, RegState::Kill)
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.addImm(ShiftImm);
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}
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LivePhysRegs LiveRegs;
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computeAndAddLiveIns(LiveRegs, *loop1MBB);
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computeAndAddLiveIns(LiveRegs, *loop2MBB);
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computeAndAddLiveIns(LiveRegs, *sinkMBB);
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computeAndAddLiveIns(LiveRegs, *exitMBB);
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NMBBI = BB.end();
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I->eraseFromParent();
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return true;
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}
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bool MipsExpandPseudo::expandAtomicCmpSwap(MachineBasicBlock &BB,
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MachineBasicBlock::iterator I,
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MachineBasicBlock::iterator &NMBBI) {
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const unsigned Size =
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I->getOpcode() == Mips::ATOMIC_CMP_SWAP_I32_POSTRA ? 4 : 8;
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MachineFunction *MF = BB.getParent();
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const bool ArePtrs64bit = STI->getABI().ArePtrs64bit();
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DebugLoc DL = I->getDebugLoc();
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unsigned LL, SC, ZERO, BNE, BEQ, MOVE;
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if (Size == 4) {
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if (STI->inMicroMipsMode()) {
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LL = STI->hasMips32r6() ? Mips::LL_MMR6 : Mips::LL_MM;
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SC = STI->hasMips32r6() ? Mips::SC_MMR6 : Mips::SC_MM;
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BNE = STI->hasMips32r6() ? Mips::BNEC_MMR6 : Mips::BNE_MM;
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BEQ = STI->hasMips32r6() ? Mips::BEQC_MMR6 : Mips::BEQ_MM;
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} else {
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LL = STI->hasMips32r6()
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? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6)
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: (ArePtrs64bit ? Mips::LL64 : Mips::LL);
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SC = STI->hasMips32r6()
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? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6)
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: (ArePtrs64bit ? Mips::SC64 : Mips::SC);
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BNE = Mips::BNE;
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BEQ = Mips::BEQ;
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}
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ZERO = Mips::ZERO;
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MOVE = Mips::OR;
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} else {
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LL = STI->hasMips64r6() ? Mips::LLD_R6 : Mips::LLD;
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SC = STI->hasMips64r6() ? Mips::SCD_R6 : Mips::SCD;
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ZERO = Mips::ZERO_64;
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BNE = Mips::BNE64;
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BEQ = Mips::BEQ64;
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MOVE = Mips::OR64;
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}
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unsigned Dest = I->getOperand(0).getReg();
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unsigned Ptr = I->getOperand(1).getReg();
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unsigned OldVal = I->getOperand(2).getReg();
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unsigned NewVal = I->getOperand(3).getReg();
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unsigned Scratch = I->getOperand(4).getReg();
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// insert new blocks after the current block
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const BasicBlock *LLVM_BB = BB.getBasicBlock();
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MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
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MachineFunction::iterator It = ++BB.getIterator();
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MF->insert(It, loop1MBB);
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MF->insert(It, loop2MBB);
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MF->insert(It, exitMBB);
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// Transfer the remainder of BB and its successor edges to exitMBB.
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exitMBB->splice(exitMBB->begin(), &BB,
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std::next(MachineBasicBlock::iterator(I)), BB.end());
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exitMBB->transferSuccessorsAndUpdatePHIs(&BB);
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// thisMBB:
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// ...
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// fallthrough --> loop1MBB
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BB.addSuccessor(loop1MBB, BranchProbability::getOne());
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loop1MBB->addSuccessor(exitMBB);
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loop1MBB->addSuccessor(loop2MBB);
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loop1MBB->normalizeSuccProbs();
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loop2MBB->addSuccessor(loop1MBB);
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loop2MBB->addSuccessor(exitMBB);
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loop2MBB->normalizeSuccProbs();
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// loop1MBB:
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// ll dest, 0(ptr)
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// bne dest, oldval, exitMBB
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BuildMI(loop1MBB, DL, TII->get(LL), Dest).addReg(Ptr).addImm(0);
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BuildMI(loop1MBB, DL, TII->get(BNE))
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.addReg(Dest, RegState::Kill).addReg(OldVal).addMBB(exitMBB);
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// loop2MBB:
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// move scratch, NewVal
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// sc Scratch, Scratch, 0(ptr)
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// beq Scratch, $0, loop1MBB
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BuildMI(loop2MBB, DL, TII->get(MOVE), Scratch).addReg(NewVal).addReg(ZERO);
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BuildMI(loop2MBB, DL, TII->get(SC), Scratch)
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.addReg(Scratch).addReg(Ptr).addImm(0);
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BuildMI(loop2MBB, DL, TII->get(BEQ))
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.addReg(Scratch, RegState::Kill).addReg(ZERO).addMBB(loop1MBB);
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LivePhysRegs LiveRegs;
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computeAndAddLiveIns(LiveRegs, *loop1MBB);
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computeAndAddLiveIns(LiveRegs, *loop2MBB);
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computeAndAddLiveIns(LiveRegs, *exitMBB);
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NMBBI = BB.end();
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I->eraseFromParent();
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return true;
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}
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bool MipsExpandPseudo::expandAtomicBinOpSubword(
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MachineBasicBlock &BB, MachineBasicBlock::iterator I,
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MachineBasicBlock::iterator &NMBBI) {
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MachineFunction *MF = BB.getParent();
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const bool ArePtrs64bit = STI->getABI().ArePtrs64bit();
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DebugLoc DL = I->getDebugLoc();
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unsigned LL, SC;
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unsigned BEQ = Mips::BEQ;
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unsigned SEOp = Mips::SEH;
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if (STI->inMicroMipsMode()) {
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LL = STI->hasMips32r6() ? Mips::LL_MMR6 : Mips::LL_MM;
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SC = STI->hasMips32r6() ? Mips::SC_MMR6 : Mips::SC_MM;
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BEQ = STI->hasMips32r6() ? Mips::BEQC_MMR6 : Mips::BEQ_MM;
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} else {
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LL = STI->hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6)
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: (ArePtrs64bit ? Mips::LL64 : Mips::LL);
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SC = STI->hasMips32r6() ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6)
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: (ArePtrs64bit ? Mips::SC64 : Mips::SC);
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}
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bool IsSwap = false;
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bool IsNand = false;
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unsigned Opcode = 0;
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switch (I->getOpcode()) {
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case Mips::ATOMIC_LOAD_NAND_I8_POSTRA:
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SEOp = Mips::SEB;
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LLVM_FALLTHROUGH;
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case Mips::ATOMIC_LOAD_NAND_I16_POSTRA:
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IsNand = true;
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break;
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case Mips::ATOMIC_SWAP_I8_POSTRA:
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SEOp = Mips::SEB;
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LLVM_FALLTHROUGH;
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case Mips::ATOMIC_SWAP_I16_POSTRA:
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IsSwap = true;
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break;
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case Mips::ATOMIC_LOAD_ADD_I8_POSTRA:
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SEOp = Mips::SEB;
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LLVM_FALLTHROUGH;
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case Mips::ATOMIC_LOAD_ADD_I16_POSTRA:
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Opcode = Mips::ADDu;
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break;
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case Mips::ATOMIC_LOAD_SUB_I8_POSTRA:
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SEOp = Mips::SEB;
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LLVM_FALLTHROUGH;
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case Mips::ATOMIC_LOAD_SUB_I16_POSTRA:
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Opcode = Mips::SUBu;
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break;
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case Mips::ATOMIC_LOAD_AND_I8_POSTRA:
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SEOp = Mips::SEB;
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LLVM_FALLTHROUGH;
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case Mips::ATOMIC_LOAD_AND_I16_POSTRA:
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Opcode = Mips::AND;
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break;
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case Mips::ATOMIC_LOAD_OR_I8_POSTRA:
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SEOp = Mips::SEB;
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LLVM_FALLTHROUGH;
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case Mips::ATOMIC_LOAD_OR_I16_POSTRA:
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Opcode = Mips::OR;
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break;
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case Mips::ATOMIC_LOAD_XOR_I8_POSTRA:
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SEOp = Mips::SEB;
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LLVM_FALLTHROUGH;
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case Mips::ATOMIC_LOAD_XOR_I16_POSTRA:
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Opcode = Mips::XOR;
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break;
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default:
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llvm_unreachable("Unknown subword atomic pseudo for expansion!");
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}
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unsigned Dest = I->getOperand(0).getReg();
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unsigned Ptr = I->getOperand(1).getReg();
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unsigned Incr = I->getOperand(2).getReg();
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unsigned Mask = I->getOperand(3).getReg();
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unsigned Mask2 = I->getOperand(4).getReg();
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unsigned ShiftAmnt = I->getOperand(5).getReg();
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unsigned OldVal = I->getOperand(6).getReg();
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unsigned BinOpRes = I->getOperand(7).getReg();
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unsigned StoreVal = I->getOperand(8).getReg();
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const BasicBlock *LLVM_BB = BB.getBasicBlock();
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MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
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MachineFunction::iterator It = ++BB.getIterator();
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MF->insert(It, loopMBB);
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MF->insert(It, sinkMBB);
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MF->insert(It, exitMBB);
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exitMBB->splice(exitMBB->begin(), &BB, std::next(I), BB.end());
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exitMBB->transferSuccessorsAndUpdatePHIs(&BB);
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BB.addSuccessor(loopMBB, BranchProbability::getOne());
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loopMBB->addSuccessor(sinkMBB);
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loopMBB->addSuccessor(loopMBB);
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loopMBB->normalizeSuccProbs();
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BuildMI(loopMBB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
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if (IsNand) {
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// and andres, oldval, incr2
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// nor binopres, $0, andres
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// and newval, binopres, mask
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BuildMI(loopMBB, DL, TII->get(Mips::AND), BinOpRes)
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.addReg(OldVal)
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.addReg(Incr);
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BuildMI(loopMBB, DL, TII->get(Mips::NOR), BinOpRes)
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.addReg(Mips::ZERO)
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.addReg(BinOpRes);
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BuildMI(loopMBB, DL, TII->get(Mips::AND), BinOpRes)
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.addReg(BinOpRes)
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.addReg(Mask);
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} else if (!IsSwap) {
|
|
// <binop> binopres, oldval, incr2
|
|
// and newval, binopres, mask
|
|
BuildMI(loopMBB, DL, TII->get(Opcode), BinOpRes)
|
|
.addReg(OldVal)
|
|
.addReg(Incr);
|
|
BuildMI(loopMBB, DL, TII->get(Mips::AND), BinOpRes)
|
|
.addReg(BinOpRes)
|
|
.addReg(Mask);
|
|
} else { // atomic.swap
|
|
// and newval, incr2, mask
|
|
BuildMI(loopMBB, DL, TII->get(Mips::AND), BinOpRes)
|
|
.addReg(Incr)
|
|
.addReg(Mask);
|
|
}
|
|
|
|
// and StoreVal, OlddVal, Mask2
|
|
// or StoreVal, StoreVal, BinOpRes
|
|
// StoreVal<tied1> = sc StoreVal, 0(Ptr)
|
|
// beq StoreVal, zero, loopMBB
|
|
BuildMI(loopMBB, DL, TII->get(Mips::AND), StoreVal)
|
|
.addReg(OldVal).addReg(Mask2);
|
|
BuildMI(loopMBB, DL, TII->get(Mips::OR), StoreVal)
|
|
.addReg(StoreVal).addReg(BinOpRes);
|
|
BuildMI(loopMBB, DL, TII->get(SC), StoreVal)
|
|
.addReg(StoreVal).addReg(Ptr).addImm(0);
|
|
BuildMI(loopMBB, DL, TII->get(BEQ))
|
|
.addReg(StoreVal).addReg(Mips::ZERO).addMBB(loopMBB);
|
|
|
|
// sinkMBB:
|
|
// and maskedoldval1,oldval,mask
|
|
// srl srlres,maskedoldval1,shiftamt
|
|
// sign_extend dest,srlres
|
|
|
|
sinkMBB->addSuccessor(exitMBB, BranchProbability::getOne());
|
|
|
|
BuildMI(sinkMBB, DL, TII->get(Mips::AND), Dest)
|
|
.addReg(OldVal).addReg(Mask);
|
|
BuildMI(sinkMBB, DL, TII->get(Mips::SRLV), Dest)
|
|
.addReg(Dest).addReg(ShiftAmnt);
|
|
|
|
if (STI->hasMips32r2()) {
|
|
BuildMI(sinkMBB, DL, TII->get(SEOp), Dest).addReg(Dest);
|
|
} else {
|
|
const unsigned ShiftImm = SEOp == Mips::SEH ? 16 : 24;
|
|
BuildMI(sinkMBB, DL, TII->get(Mips::SLL), Dest)
|
|
.addReg(Dest, RegState::Kill)
|
|
.addImm(ShiftImm);
|
|
BuildMI(sinkMBB, DL, TII->get(Mips::SRA), Dest)
|
|
.addReg(Dest, RegState::Kill)
|
|
.addImm(ShiftImm);
|
|
}
|
|
|
|
LivePhysRegs LiveRegs;
|
|
computeAndAddLiveIns(LiveRegs, *loopMBB);
|
|
computeAndAddLiveIns(LiveRegs, *sinkMBB);
|
|
computeAndAddLiveIns(LiveRegs, *exitMBB);
|
|
|
|
NMBBI = BB.end();
|
|
I->eraseFromParent();
|
|
|
|
return true;
|
|
}
|
|
|
|
bool MipsExpandPseudo::expandAtomicBinOp(MachineBasicBlock &BB,
|
|
MachineBasicBlock::iterator I,
|
|
MachineBasicBlock::iterator &NMBBI,
|
|
unsigned Size) {
|
|
MachineFunction *MF = BB.getParent();
|
|
|
|
const bool ArePtrs64bit = STI->getABI().ArePtrs64bit();
|
|
DebugLoc DL = I->getDebugLoc();
|
|
|
|
unsigned LL, SC, ZERO, BEQ;
|
|
|
|
if (Size == 4) {
|
|
if (STI->inMicroMipsMode()) {
|
|
LL = STI->hasMips32r6() ? Mips::LL_MMR6 : Mips::LL_MM;
|
|
SC = STI->hasMips32r6() ? Mips::SC_MMR6 : Mips::SC_MM;
|
|
BEQ = STI->hasMips32r6() ? Mips::BEQC_MMR6 : Mips::BEQ_MM;
|
|
} else {
|
|
LL = STI->hasMips32r6()
|
|
? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6)
|
|
: (ArePtrs64bit ? Mips::LL64 : Mips::LL);
|
|
SC = STI->hasMips32r6()
|
|
? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6)
|
|
: (ArePtrs64bit ? Mips::SC64 : Mips::SC);
|
|
BEQ = Mips::BEQ;
|
|
}
|
|
|
|
ZERO = Mips::ZERO;
|
|
} else {
|
|
LL = STI->hasMips64r6() ? Mips::LLD_R6 : Mips::LLD;
|
|
SC = STI->hasMips64r6() ? Mips::SCD_R6 : Mips::SCD;
|
|
ZERO = Mips::ZERO_64;
|
|
BEQ = Mips::BEQ64;
|
|
}
|
|
|
|
unsigned OldVal = I->getOperand(0).getReg();
|
|
unsigned Ptr = I->getOperand(1).getReg();
|
|
unsigned Incr = I->getOperand(2).getReg();
|
|
unsigned Scratch = I->getOperand(3).getReg();
|
|
|
|
unsigned Opcode = 0;
|
|
unsigned OR = 0;
|
|
unsigned AND = 0;
|
|
unsigned NOR = 0;
|
|
bool IsNand = false;
|
|
switch (I->getOpcode()) {
|
|
case Mips::ATOMIC_LOAD_ADD_I32_POSTRA:
|
|
Opcode = Mips::ADDu;
|
|
break;
|
|
case Mips::ATOMIC_LOAD_SUB_I32_POSTRA:
|
|
Opcode = Mips::SUBu;
|
|
break;
|
|
case Mips::ATOMIC_LOAD_AND_I32_POSTRA:
|
|
Opcode = Mips::AND;
|
|
break;
|
|
case Mips::ATOMIC_LOAD_OR_I32_POSTRA:
|
|
Opcode = Mips::OR;
|
|
break;
|
|
case Mips::ATOMIC_LOAD_XOR_I32_POSTRA:
|
|
Opcode = Mips::XOR;
|
|
break;
|
|
case Mips::ATOMIC_LOAD_NAND_I32_POSTRA:
|
|
IsNand = true;
|
|
AND = Mips::AND;
|
|
NOR = Mips::NOR;
|
|
break;
|
|
case Mips::ATOMIC_SWAP_I32_POSTRA:
|
|
OR = Mips::OR;
|
|
break;
|
|
case Mips::ATOMIC_LOAD_ADD_I64_POSTRA:
|
|
Opcode = Mips::DADDu;
|
|
break;
|
|
case Mips::ATOMIC_LOAD_SUB_I64_POSTRA:
|
|
Opcode = Mips::DSUBu;
|
|
break;
|
|
case Mips::ATOMIC_LOAD_AND_I64_POSTRA:
|
|
Opcode = Mips::AND64;
|
|
break;
|
|
case Mips::ATOMIC_LOAD_OR_I64_POSTRA:
|
|
Opcode = Mips::OR64;
|
|
break;
|
|
case Mips::ATOMIC_LOAD_XOR_I64_POSTRA:
|
|
Opcode = Mips::XOR64;
|
|
break;
|
|
case Mips::ATOMIC_LOAD_NAND_I64_POSTRA:
|
|
IsNand = true;
|
|
AND = Mips::AND64;
|
|
NOR = Mips::NOR64;
|
|
break;
|
|
case Mips::ATOMIC_SWAP_I64_POSTRA:
|
|
OR = Mips::OR64;
|
|
break;
|
|
default:
|
|
llvm_unreachable("Unknown pseudo atomic!");
|
|
}
|
|
|
|
const BasicBlock *LLVM_BB = BB.getBasicBlock();
|
|
MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
|
|
MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
|
|
MachineFunction::iterator It = ++BB.getIterator();
|
|
MF->insert(It, loopMBB);
|
|
MF->insert(It, exitMBB);
|
|
|
|
exitMBB->splice(exitMBB->begin(), &BB, std::next(I), BB.end());
|
|
exitMBB->transferSuccessorsAndUpdatePHIs(&BB);
|
|
|
|
BB.addSuccessor(loopMBB, BranchProbability::getOne());
|
|
loopMBB->addSuccessor(exitMBB);
|
|
loopMBB->addSuccessor(loopMBB);
|
|
loopMBB->normalizeSuccProbs();
|
|
|
|
BuildMI(loopMBB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
|
|
assert((OldVal != Ptr) && "Clobbered the wrong ptr reg!");
|
|
assert((OldVal != Incr) && "Clobbered the wrong reg!");
|
|
if (Opcode) {
|
|
BuildMI(loopMBB, DL, TII->get(Opcode), Scratch).addReg(OldVal).addReg(Incr);
|
|
} else if (IsNand) {
|
|
assert(AND && NOR &&
|
|
"Unknown nand instruction for atomic pseudo expansion");
|
|
BuildMI(loopMBB, DL, TII->get(AND), Scratch).addReg(OldVal).addReg(Incr);
|
|
BuildMI(loopMBB, DL, TII->get(NOR), Scratch).addReg(ZERO).addReg(Scratch);
|
|
} else {
|
|
assert(OR && "Unknown instruction for atomic pseudo expansion!");
|
|
BuildMI(loopMBB, DL, TII->get(OR), Scratch).addReg(Incr).addReg(ZERO);
|
|
}
|
|
|
|
BuildMI(loopMBB, DL, TII->get(SC), Scratch).addReg(Scratch).addReg(Ptr).addImm(0);
|
|
BuildMI(loopMBB, DL, TII->get(BEQ)).addReg(Scratch).addReg(ZERO).addMBB(loopMBB);
|
|
|
|
NMBBI = BB.end();
|
|
I->eraseFromParent();
|
|
|
|
LivePhysRegs LiveRegs;
|
|
computeAndAddLiveIns(LiveRegs, *loopMBB);
|
|
computeAndAddLiveIns(LiveRegs, *exitMBB);
|
|
|
|
return true;
|
|
}
|
|
|
|
bool MipsExpandPseudo::expandMI(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MBBI,
|
|
MachineBasicBlock::iterator &NMBB) {
|
|
|
|
bool Modified = false;
|
|
|
|
switch (MBBI->getOpcode()) {
|
|
case Mips::ATOMIC_CMP_SWAP_I32_POSTRA:
|
|
case Mips::ATOMIC_CMP_SWAP_I64_POSTRA:
|
|
return expandAtomicCmpSwap(MBB, MBBI, NMBB);
|
|
case Mips::ATOMIC_CMP_SWAP_I8_POSTRA:
|
|
case Mips::ATOMIC_CMP_SWAP_I16_POSTRA:
|
|
return expandAtomicCmpSwapSubword(MBB, MBBI, NMBB);
|
|
case Mips::ATOMIC_SWAP_I8_POSTRA:
|
|
case Mips::ATOMIC_SWAP_I16_POSTRA:
|
|
case Mips::ATOMIC_LOAD_NAND_I8_POSTRA:
|
|
case Mips::ATOMIC_LOAD_NAND_I16_POSTRA:
|
|
case Mips::ATOMIC_LOAD_ADD_I8_POSTRA:
|
|
case Mips::ATOMIC_LOAD_ADD_I16_POSTRA:
|
|
case Mips::ATOMIC_LOAD_SUB_I8_POSTRA:
|
|
case Mips::ATOMIC_LOAD_SUB_I16_POSTRA:
|
|
case Mips::ATOMIC_LOAD_AND_I8_POSTRA:
|
|
case Mips::ATOMIC_LOAD_AND_I16_POSTRA:
|
|
case Mips::ATOMIC_LOAD_OR_I8_POSTRA:
|
|
case Mips::ATOMIC_LOAD_OR_I16_POSTRA:
|
|
case Mips::ATOMIC_LOAD_XOR_I8_POSTRA:
|
|
case Mips::ATOMIC_LOAD_XOR_I16_POSTRA:
|
|
return expandAtomicBinOpSubword(MBB, MBBI, NMBB);
|
|
case Mips::ATOMIC_LOAD_ADD_I32_POSTRA:
|
|
case Mips::ATOMIC_LOAD_SUB_I32_POSTRA:
|
|
case Mips::ATOMIC_LOAD_AND_I32_POSTRA:
|
|
case Mips::ATOMIC_LOAD_OR_I32_POSTRA:
|
|
case Mips::ATOMIC_LOAD_XOR_I32_POSTRA:
|
|
case Mips::ATOMIC_LOAD_NAND_I32_POSTRA:
|
|
case Mips::ATOMIC_SWAP_I32_POSTRA:
|
|
return expandAtomicBinOp(MBB, MBBI, NMBB, 4);
|
|
case Mips::ATOMIC_LOAD_ADD_I64_POSTRA:
|
|
case Mips::ATOMIC_LOAD_SUB_I64_POSTRA:
|
|
case Mips::ATOMIC_LOAD_AND_I64_POSTRA:
|
|
case Mips::ATOMIC_LOAD_OR_I64_POSTRA:
|
|
case Mips::ATOMIC_LOAD_XOR_I64_POSTRA:
|
|
case Mips::ATOMIC_LOAD_NAND_I64_POSTRA:
|
|
case Mips::ATOMIC_SWAP_I64_POSTRA:
|
|
return expandAtomicBinOp(MBB, MBBI, NMBB, 8);
|
|
default:
|
|
return Modified;
|
|
}
|
|
}
|
|
|
|
bool MipsExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
|
|
bool Modified = false;
|
|
|
|
MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
|
|
while (MBBI != E) {
|
|
MachineBasicBlock::iterator NMBBI = std::next(MBBI);
|
|
Modified |= expandMI(MBB, MBBI, NMBBI);
|
|
MBBI = NMBBI;
|
|
}
|
|
|
|
return Modified;
|
|
}
|
|
|
|
bool MipsExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
|
|
STI = &static_cast<const MipsSubtarget &>(MF.getSubtarget());
|
|
TII = STI->getInstrInfo();
|
|
|
|
bool Modified = false;
|
|
for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E;
|
|
++MFI)
|
|
Modified |= expandMBB(*MFI);
|
|
|
|
if (Modified)
|
|
MF.RenumberBlocks();
|
|
|
|
return Modified;
|
|
}
|
|
|
|
/// createMipsExpandPseudoPass - returns an instance of the pseudo instruction
|
|
/// expansion pass.
|
|
FunctionPass *llvm::createMipsExpandPseudoPass() {
|
|
return new MipsExpandPseudo();
|
|
}
|