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208 lines
7.6 KiB
TableGen
208 lines
7.6 KiB
TableGen
//===-- MipsMTInstrInfo.td - Mips MT Instruction Infos -----*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the MIPS MT ASE as defined by MD00378 1.12.
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//
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// TODO: Add support for the microMIPS encodings for the MT ASE and add the
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// instruction mappings.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// MIPS MT Instruction Encodings
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//===----------------------------------------------------------------------===//
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class DMT_ENC : COP0_MFMC0_MT<FIELD5_1_DMT_EMT, FIELD5_2_DMT_EMT,
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OPCODE_SC_D>;
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class EMT_ENC : COP0_MFMC0_MT<FIELD5_1_DMT_EMT, FIELD5_2_DMT_EMT,
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OPCODE_SC_E>;
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class DVPE_ENC : COP0_MFMC0_MT<FIELD5_1_2_DVPE_EVPE, FIELD5_1_2_DVPE_EVPE,
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OPCODE_SC_D>;
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class EVPE_ENC : COP0_MFMC0_MT<FIELD5_1_2_DVPE_EVPE, FIELD5_1_2_DVPE_EVPE,
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OPCODE_SC_E>;
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class FORK_ENC : SPECIAL3_MT_FORK;
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class YIELD_ENC : SPECIAL3_MT_YIELD;
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class MFTR_ENC : COP0_MFTTR_MT<FIELD5_MFTR>;
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class MTTR_ENC : COP0_MFTTR_MT<FIELD5_MTTR>;
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//===----------------------------------------------------------------------===//
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// MIPS MT Instruction Descriptions
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//===----------------------------------------------------------------------===//
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class MT_1R_DESC_BASE<string instr_asm, InstrItinClass Itin = NoItinerary> {
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dag OutOperandList = (outs GPR32Opnd:$rt);
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dag InOperandList = (ins);
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string AsmString = !strconcat(instr_asm, "\t$rt");
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list<dag> Pattern = [];
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InstrItinClass Itinerary = Itin;
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}
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class MFTR_DESC {
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dag OutOperandList = (outs GPR32Opnd:$rd);
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dag InOperandList = (ins GPR32Opnd:$rt, uimm1:$u, uimm3:$sel, uimm1:$h);
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string AsmString = "mftr\t$rd, $rt, $u, $sel, $h";
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list<dag> Pattern = [];
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InstrItinClass Itinerary = II_MFTR;
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}
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class MTTR_DESC {
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dag OutOperandList = (outs GPR32Opnd:$rd);
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dag InOperandList = (ins GPR32Opnd:$rt, uimm1:$u, uimm3:$sel, uimm1:$h);
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string AsmString = "mttr\t$rt, $rd, $u, $sel, $h";
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list<dag> Pattern = [];
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InstrItinClass Itinerary = II_MTTR;
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}
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class FORK_DESC {
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dag OutOperandList = (outs GPR32Opnd:$rs, GPR32Opnd:$rd);
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dag InOperandList = (ins GPR32Opnd:$rt);
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string AsmString = "fork\t$rd, $rs, $rt";
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list<dag> Pattern = [];
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InstrItinClass Itinerary = II_FORK;
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}
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class YIELD_DESC {
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dag OutOperandList = (outs GPR32Opnd:$rd);
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dag InOperandList = (ins GPR32Opnd:$rs);
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string AsmString = "yield\t$rd, $rs";
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list<dag> Pattern = [];
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InstrItinClass Itinerary = II_YIELD;
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}
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class DMT_DESC : MT_1R_DESC_BASE<"dmt", II_DMT>;
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class EMT_DESC : MT_1R_DESC_BASE<"emt", II_EMT>;
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class DVPE_DESC : MT_1R_DESC_BASE<"dvpe", II_DVPE>;
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class EVPE_DESC : MT_1R_DESC_BASE<"evpe", II_EVPE>;
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//===----------------------------------------------------------------------===//
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// MIPS MT Instruction Definitions
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//===----------------------------------------------------------------------===//
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let hasSideEffects = 1, isNotDuplicable = 1,
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AdditionalPredicates = [NotInMicroMips] in {
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def DMT : DMT_ENC, DMT_DESC, ASE_MT;
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def EMT : EMT_ENC, EMT_DESC, ASE_MT;
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def DVPE : DVPE_ENC, DVPE_DESC, ASE_MT;
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def EVPE : EVPE_ENC, EVPE_DESC, ASE_MT;
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def FORK : FORK_ENC, FORK_DESC, ASE_MT;
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def YIELD : YIELD_ENC, YIELD_DESC, ASE_MT;
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def MFTR : MFTR_ENC, MFTR_DESC, ASE_MT;
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def MTTR : MTTR_ENC, MTTR_DESC, ASE_MT;
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}
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//===----------------------------------------------------------------------===//
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// MIPS MT Pseudo Instructions - used to support mtfr & mttr aliases.
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//===----------------------------------------------------------------------===//
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def MFTC0 : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins COP0Opnd:$rt,
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uimm3:$sel),
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"mftc0 $rd, $rt, $sel">, ASE_MT;
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def MFTGPR : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rt,
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uimm3:$sel),
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"mftgpr $rd, $rt">, ASE_MT;
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def MFTLO : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins ACC64DSPOpnd:$ac),
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"mftlo $rt, $ac">, ASE_MT;
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def MFTHI : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins ACC64DSPOpnd:$ac),
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"mfthi $rt, $ac">, ASE_MT;
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def MFTACX : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins ACC64DSPOpnd:$ac),
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"mftacx $rt, $ac">, ASE_MT;
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def MFTDSP : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins),
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"mftdsp $rt">, ASE_MT;
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def MFTC1 : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins FGR32Opnd:$ft),
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"mftc1 $rt, $ft">, ASE_MT;
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def MFTHC1 : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins FGR32Opnd:$ft),
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"mfthc1 $rt, $ft">, ASE_MT;
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def CFTC1 : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins FGRCCOpnd:$ft),
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"cftc1 $rt, $ft">, ASE_MT;
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def MTTC0 : MipsAsmPseudoInst<(outs COP0Opnd:$rd), (ins GPR32Opnd:$rt,
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uimm3:$sel),
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"mttc0 $rt, $rd, $sel">, ASE_MT;
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def MTTGPR : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins GPR32Opnd:$rd),
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"mttgpr $rd, $rt">, ASE_MT;
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def MTTLO : MipsAsmPseudoInst<(outs ACC64DSPOpnd:$ac), (ins GPR32Opnd:$rt),
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"mttlo $rt, $ac">, ASE_MT;
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def MTTHI : MipsAsmPseudoInst<(outs ACC64DSPOpnd:$ac), (ins GPR32Opnd:$rt),
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"mtthi $rt, $ac">, ASE_MT;
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def MTTACX : MipsAsmPseudoInst<(outs ACC64DSPOpnd:$ac), (ins GPR32Opnd:$rt),
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"mttacx $rt, $ac">, ASE_MT;
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def MTTDSP : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rt),
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"mttdsp $rt">, ASE_MT;
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def MTTC1 : MipsAsmPseudoInst<(outs FGR32Opnd:$ft), (ins GPR32Opnd:$rt),
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"mttc1 $rt, $ft">, ASE_MT;
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def MTTHC1 : MipsAsmPseudoInst<(outs FGR32Opnd:$ft), (ins GPR32Opnd:$rt),
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"mtthc1 $rt, $ft">, ASE_MT;
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def CTTC1 : MipsAsmPseudoInst<(outs FGRCCOpnd:$ft), (ins GPR32Opnd:$rt),
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"cttc1 $rt, $ft">, ASE_MT;
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//===----------------------------------------------------------------------===//
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// MIPS MT Instruction Definitions
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//===----------------------------------------------------------------------===//
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let AdditionalPredicates = [NotInMicroMips] in {
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def : MipsInstAlias<"dmt", (DMT ZERO), 1>, ASE_MT;
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def : MipsInstAlias<"emt", (EMT ZERO), 1>, ASE_MT;
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def : MipsInstAlias<"dvpe", (DVPE ZERO), 1>, ASE_MT;
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def : MipsInstAlias<"evpe", (EVPE ZERO), 1>, ASE_MT;
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def : MipsInstAlias<"yield $rs", (YIELD ZERO, GPR32Opnd:$rs), 1>, ASE_MT;
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def : MipsInstAlias<"mftc0 $rd, $rt", (MFTC0 GPR32Opnd:$rd, COP0Opnd:$rt, 0),
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1>, ASE_MT;
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def : MipsInstAlias<"mftlo $rt", (MFTLO GPR32Opnd:$rt, AC0), 1>, ASE_MT;
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def : MipsInstAlias<"mfthi $rt", (MFTHI GPR32Opnd:$rt, AC0), 1>, ASE_MT;
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def : MipsInstAlias<"mftacx $rt", (MFTACX GPR32Opnd:$rt, AC0), 1>, ASE_MT;
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def : MipsInstAlias<"mttc0 $rd, $rt", (MTTC0 COP0Opnd:$rt, GPR32Opnd:$rd, 0),
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1>, ASE_MT;
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def : MipsInstAlias<"mttlo $rt", (MTTLO AC0, GPR32Opnd:$rt), 1>, ASE_MT;
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def : MipsInstAlias<"mtthi $rt", (MTTHI AC0, GPR32Opnd:$rt), 1>, ASE_MT;
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def : MipsInstAlias<"mttacx $rt", (MTTACX AC0, GPR32Opnd:$rt), 1>, ASE_MT;
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}
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