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32aacd5feb
lowering to support both anyext and zext and to custom lower for many different microarchitectures. Using this allows us to get *exactly* the right code for zext and anyext shuffles in all the vector sizes. For v16i8, the improvement is *huge*. The new SSE2 test case added I refused to add before this because it was sooooo muny instructions. llvm-svn: 218143
19 lines
610 B
LLVM
19 lines
610 B
LLVM
; RUN: llc < %s -mcpu=x86-64 -x86-experimental-vector-widening-legalization -x86-experimental-vector-shuffle-lowering | FileCheck %s
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-unknown"
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define <4 x i32> @zext_v4i8_to_v4i32(<4 x i8>* %ptr) {
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; CHECK-LABEL: zext_v4i8_to_v4i32:
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;
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; CHECK: movd (%{{.*}}), %[[X:xmm[0-9]+]]
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; CHECK-NEXT: pxor %[[Z:xmm[0-9]+]], %[[Z]]
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; CHECK-NEXT: punpcklbw %[[Z]], %[[X]]
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; CHECK-NEXT: punpcklwd %[[Z]], %[[X]]
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; CHECK-NEXT: ret
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%val = load <4 x i8>* %ptr
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%ext = zext <4 x i8> %val to <4 x i32>
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ret <4 x i32> %ext
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}
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