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to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
488 lines
25 KiB
TableGen
488 lines
25 KiB
TableGen
//===-- X86InstrXOP.td - XOP Instruction Set ---------------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes XOP (eXtended OPerations)
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//
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//===----------------------------------------------------------------------===//
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multiclass xop2op<bits<8> opc, string OpcodeStr, Intrinsic Int> {
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def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (Int VR128:$src))]>, XOP, Sched<[SchedWritePHAdd.XMM]>;
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def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (Int (load addr:$src)))]>, XOP,
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Sched<[SchedWritePHAdd.XMM.Folded, SchedWritePHAdd.XMM.ReadAfterFold]>;
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}
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let ExeDomain = SSEPackedInt in {
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defm VPHSUBWD : xop2op<0xE2, "vphsubwd", int_x86_xop_vphsubwd>;
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defm VPHSUBDQ : xop2op<0xE3, "vphsubdq", int_x86_xop_vphsubdq>;
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defm VPHSUBBW : xop2op<0xE1, "vphsubbw", int_x86_xop_vphsubbw>;
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defm VPHADDWQ : xop2op<0xC7, "vphaddwq", int_x86_xop_vphaddwq>;
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defm VPHADDWD : xop2op<0xC6, "vphaddwd", int_x86_xop_vphaddwd>;
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defm VPHADDUWQ : xop2op<0xD7, "vphadduwq", int_x86_xop_vphadduwq>;
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defm VPHADDUWD : xop2op<0xD6, "vphadduwd", int_x86_xop_vphadduwd>;
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defm VPHADDUDQ : xop2op<0xDB, "vphaddudq", int_x86_xop_vphaddudq>;
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defm VPHADDUBW : xop2op<0xD1, "vphaddubw", int_x86_xop_vphaddubw>;
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defm VPHADDUBQ : xop2op<0xD3, "vphaddubq", int_x86_xop_vphaddubq>;
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defm VPHADDUBD : xop2op<0xD2, "vphaddubd", int_x86_xop_vphaddubd>;
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defm VPHADDDQ : xop2op<0xCB, "vphadddq", int_x86_xop_vphadddq>;
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defm VPHADDBW : xop2op<0xC1, "vphaddbw", int_x86_xop_vphaddbw>;
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defm VPHADDBQ : xop2op<0xC3, "vphaddbq", int_x86_xop_vphaddbq>;
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defm VPHADDBD : xop2op<0xC2, "vphaddbd", int_x86_xop_vphaddbd>;
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}
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// Scalar load 2 addr operand instructions
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multiclass xop2opsld<bits<8> opc, string OpcodeStr, Intrinsic Int,
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Operand memop, ComplexPattern mem_cpat,
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X86FoldableSchedWrite sched> {
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def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (Int VR128:$src))]>, XOP, Sched<[sched]>;
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def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins memop:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (Int mem_cpat:$src))]>, XOP,
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Sched<[sched.Folded, sched.ReadAfterFold]>;
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}
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multiclass xop2op128<bits<8> opc, string OpcodeStr, Intrinsic Int,
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X86FoldableSchedWrite sched> {
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def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (Int VR128:$src))]>, XOP, Sched<[sched]>;
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def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (Int (load addr:$src)))]>, XOP,
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Sched<[sched.Folded, sched.ReadAfterFold]>;
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}
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multiclass xop2op256<bits<8> opc, string OpcodeStr, Intrinsic Int,
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X86FoldableSchedWrite sched> {
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def Yrr : IXOP<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR256:$dst, (Int VR256:$src))]>, XOP, VEX_L, Sched<[sched]>;
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def Yrm : IXOP<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR256:$dst, (Int (load addr:$src)))]>, XOP, VEX_L,
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Sched<[sched.Folded, sched.ReadAfterFold]>;
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}
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let ExeDomain = SSEPackedSingle in {
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defm VFRCZSS : xop2opsld<0x82, "vfrczss", int_x86_xop_vfrcz_ss,
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ssmem, sse_load_f32, SchedWriteFRnd.Scl>;
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defm VFRCZPS : xop2op128<0x80, "vfrczps", int_x86_xop_vfrcz_ps,
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SchedWriteFRnd.XMM>;
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defm VFRCZPS : xop2op256<0x80, "vfrczps", int_x86_xop_vfrcz_ps_256,
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SchedWriteFRnd.YMM>;
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}
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let ExeDomain = SSEPackedDouble in {
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defm VFRCZSD : xop2opsld<0x83, "vfrczsd", int_x86_xop_vfrcz_sd,
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sdmem, sse_load_f64, SchedWriteFRnd.Scl>;
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defm VFRCZPD : xop2op128<0x81, "vfrczpd", int_x86_xop_vfrcz_pd,
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SchedWriteFRnd.XMM>;
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defm VFRCZPD : xop2op256<0x81, "vfrczpd", int_x86_xop_vfrcz_pd_256,
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SchedWriteFRnd.YMM>;
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}
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multiclass xop3op<bits<8> opc, string OpcodeStr, SDNode OpNode,
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ValueType vt128, X86FoldableSchedWrite sched> {
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def rr : IXOP<opc, MRMSrcReg4VOp3, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR128:$dst,
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(vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2))))]>,
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XOP, Sched<[sched]>;
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def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR128:$dst,
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(vt128 (OpNode (vt128 VR128:$src1),
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(vt128 (load addr:$src2)))))]>,
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XOP_4V, VEX_W, Sched<[sched.Folded, sched.ReadAfterFold]>;
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def mr : IXOP<opc, MRMSrcMem4VOp3, (outs VR128:$dst),
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(ins i128mem:$src1, VR128:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR128:$dst,
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(vt128 (OpNode (vt128 (load addr:$src1)),
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(vt128 VR128:$src2))))]>,
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XOP, Sched<[sched.Folded, sched.ReadAfterFold]>;
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// For disassembler
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let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
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def rr_REV : IXOP<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[]>,
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XOP_4V, VEX_W, Sched<[sched]>, FoldGenData<NAME#rr>;
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}
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let ExeDomain = SSEPackedInt in {
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defm VPROTB : xop3op<0x90, "vprotb", rotl, v16i8, SchedWriteVarVecShift.XMM>;
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defm VPROTD : xop3op<0x92, "vprotd", rotl, v4i32, SchedWriteVarVecShift.XMM>;
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defm VPROTQ : xop3op<0x93, "vprotq", rotl, v2i64, SchedWriteVarVecShift.XMM>;
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defm VPROTW : xop3op<0x91, "vprotw", rotl, v8i16, SchedWriteVarVecShift.XMM>;
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defm VPSHAB : xop3op<0x98, "vpshab", X86vpsha, v16i8, SchedWriteVarVecShift.XMM>;
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defm VPSHAD : xop3op<0x9A, "vpshad", X86vpsha, v4i32, SchedWriteVarVecShift.XMM>;
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defm VPSHAQ : xop3op<0x9B, "vpshaq", X86vpsha, v2i64, SchedWriteVarVecShift.XMM>;
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defm VPSHAW : xop3op<0x99, "vpshaw", X86vpsha, v8i16, SchedWriteVarVecShift.XMM>;
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defm VPSHLB : xop3op<0x94, "vpshlb", X86vpshl, v16i8, SchedWriteVarVecShift.XMM>;
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defm VPSHLD : xop3op<0x96, "vpshld", X86vpshl, v4i32, SchedWriteVarVecShift.XMM>;
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defm VPSHLQ : xop3op<0x97, "vpshlq", X86vpshl, v2i64, SchedWriteVarVecShift.XMM>;
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defm VPSHLW : xop3op<0x95, "vpshlw", X86vpshl, v8i16, SchedWriteVarVecShift.XMM>;
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}
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multiclass xop3opimm<bits<8> opc, string OpcodeStr, SDNode OpNode,
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ValueType vt128, X86FoldableSchedWrite sched> {
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def ri : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, u8imm:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR128:$dst,
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(vt128 (OpNode (vt128 VR128:$src1), imm:$src2)))]>,
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XOP, Sched<[sched]>;
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def mi : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
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(ins i128mem:$src1, u8imm:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR128:$dst,
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(vt128 (OpNode (vt128 (load addr:$src1)), imm:$src2)))]>,
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XOP, Sched<[sched.Folded, sched.ReadAfterFold]>;
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}
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let ExeDomain = SSEPackedInt in {
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defm VPROTB : xop3opimm<0xC0, "vprotb", X86vrotli, v16i8,
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SchedWriteVecShiftImm.XMM>;
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defm VPROTD : xop3opimm<0xC2, "vprotd", X86vrotli, v4i32,
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SchedWriteVecShiftImm.XMM>;
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defm VPROTQ : xop3opimm<0xC3, "vprotq", X86vrotli, v2i64,
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SchedWriteVecShiftImm.XMM>;
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defm VPROTW : xop3opimm<0xC1, "vprotw", X86vrotli, v8i16,
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SchedWriteVecShiftImm.XMM>;
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}
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// Instruction where second source can be memory, but third must be register
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multiclass xop4opm2<bits<8> opc, string OpcodeStr, Intrinsic Int,
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X86FoldableSchedWrite sched> {
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let isCommutable = 1 in
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def rr : IXOPi8Reg<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set VR128:$dst,
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(Int VR128:$src1, VR128:$src2, VR128:$src3))]>, XOP_4V,
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Sched<[sched]>;
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def rm : IXOPi8Reg<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set VR128:$dst,
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(Int VR128:$src1, (load addr:$src2),
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VR128:$src3))]>, XOP_4V, Sched<[sched.Folded, sched.ReadAfterFold]>;
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}
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let ExeDomain = SSEPackedInt in {
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defm VPMADCSWD : xop4opm2<0xB6, "vpmadcswd",
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int_x86_xop_vpmadcswd, SchedWriteVecIMul.XMM>;
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defm VPMADCSSWD : xop4opm2<0xA6, "vpmadcsswd",
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int_x86_xop_vpmadcsswd, SchedWriteVecIMul.XMM>;
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defm VPMACSWW : xop4opm2<0x95, "vpmacsww",
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int_x86_xop_vpmacsww, SchedWriteVecIMul.XMM>;
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defm VPMACSWD : xop4opm2<0x96, "vpmacswd",
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int_x86_xop_vpmacswd, SchedWriteVecIMul.XMM>;
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defm VPMACSSWW : xop4opm2<0x85, "vpmacssww",
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int_x86_xop_vpmacssww, SchedWriteVecIMul.XMM>;
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defm VPMACSSWD : xop4opm2<0x86, "vpmacsswd",
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int_x86_xop_vpmacsswd, SchedWriteVecIMul.XMM>;
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defm VPMACSSDQL : xop4opm2<0x87, "vpmacssdql",
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int_x86_xop_vpmacssdql, SchedWritePMULLD.XMM>;
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defm VPMACSSDQH : xop4opm2<0x8F, "vpmacssdqh",
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int_x86_xop_vpmacssdqh, SchedWritePMULLD.XMM>;
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defm VPMACSSDD : xop4opm2<0x8E, "vpmacssdd",
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int_x86_xop_vpmacssdd, SchedWritePMULLD.XMM>;
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defm VPMACSDQL : xop4opm2<0x97, "vpmacsdql",
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int_x86_xop_vpmacsdql, SchedWritePMULLD.XMM>;
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defm VPMACSDQH : xop4opm2<0x9F, "vpmacsdqh",
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int_x86_xop_vpmacsdqh, SchedWritePMULLD.XMM>;
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defm VPMACSDD : xop4opm2<0x9E, "vpmacsdd",
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int_x86_xop_vpmacsdd, SchedWritePMULLD.XMM>;
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}
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// IFMA patterns - for cases where we can safely ignore the overflow bits from
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// the multiply or easily match with existing intrinsics.
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let Predicates = [HasXOP] in {
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def : Pat<(v8i16 (add (mul (v8i16 VR128:$src1), (v8i16 VR128:$src2)),
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(v8i16 VR128:$src3))),
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(VPMACSWWrr VR128:$src1, VR128:$src2, VR128:$src3)>;
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def : Pat<(v4i32 (add (mul (v4i32 VR128:$src1), (v4i32 VR128:$src2)),
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(v4i32 VR128:$src3))),
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(VPMACSDDrr VR128:$src1, VR128:$src2, VR128:$src3)>;
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def : Pat<(v2i64 (add (X86pmuldq (bc_v2i64 (X86PShufd (v4i32 VR128:$src1), (i8 -11))),
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(bc_v2i64 (X86PShufd (v4i32 VR128:$src2), (i8 -11)))),
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(v2i64 VR128:$src3))),
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(VPMACSDQHrr VR128:$src1, VR128:$src2, VR128:$src3)>;
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def : Pat<(v2i64 (add (X86pmuldq (v2i64 VR128:$src1), (v2i64 VR128:$src2)),
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(v2i64 VR128:$src3))),
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(VPMACSDQLrr VR128:$src1, VR128:$src2, VR128:$src3)>;
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def : Pat<(v4i32 (add (X86vpmaddwd (v8i16 VR128:$src1), (v8i16 VR128:$src2)),
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(v4i32 VR128:$src3))),
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(VPMADCSWDrr VR128:$src1, VR128:$src2, VR128:$src3)>;
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}
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// Transforms to swizzle an immediate to help matching memory operand in first
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// operand.
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def CommuteVPCOMCC : SDNodeXForm<imm, [{
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uint8_t Imm = N->getZExtValue() & 0x7;
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Imm = X86::getSwappedVPCOMImm(Imm);
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return getI8Imm(Imm, SDLoc(N));
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}]>;
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// Instruction where second source can be memory, third must be imm8
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multiclass xopvpcom<bits<8> opc, string Suffix, SDNode OpNode, ValueType vt128,
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X86FoldableSchedWrite sched> {
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let ExeDomain = SSEPackedInt in { // SSE integer instructions
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let isCommutable = 1 in
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def ri : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, XOPCC:$cc),
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!strconcat("vpcom${cc}", Suffix,
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR128:$dst,
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(vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2),
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imm:$cc)))]>,
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XOP_4V, Sched<[sched]>;
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def mi : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2, XOPCC:$cc),
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!strconcat("vpcom${cc}", Suffix,
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR128:$dst,
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(vt128 (OpNode (vt128 VR128:$src1),
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(vt128 (load addr:$src2)),
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imm:$cc)))]>,
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XOP_4V, Sched<[sched.Folded, sched.ReadAfterFold]>;
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let isAsmParserOnly = 1, hasSideEffects = 0 in {
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def ri_alt : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, u8imm:$src3),
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!strconcat("vpcom", Suffix,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[]>, XOP_4V, Sched<[sched]>, NotMemoryFoldable;
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let mayLoad = 1 in
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def mi_alt : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2, u8imm:$src3),
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!strconcat("vpcom", Suffix,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[]>, XOP_4V, Sched<[sched.Folded, sched.ReadAfterFold]>,
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NotMemoryFoldable;
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}
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}
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def : Pat<(OpNode (load addr:$src2),
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(vt128 VR128:$src1), imm:$cc),
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(!cast<Instruction>(NAME#"mi") VR128:$src1, addr:$src2,
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(CommuteVPCOMCC imm:$cc))>;
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}
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defm VPCOMB : xopvpcom<0xCC, "b", X86vpcom, v16i8, SchedWriteVecALU.XMM>;
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defm VPCOMW : xopvpcom<0xCD, "w", X86vpcom, v8i16, SchedWriteVecALU.XMM>;
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defm VPCOMD : xopvpcom<0xCE, "d", X86vpcom, v4i32, SchedWriteVecALU.XMM>;
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defm VPCOMQ : xopvpcom<0xCF, "q", X86vpcom, v2i64, SchedWriteVecALU.XMM>;
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defm VPCOMUB : xopvpcom<0xEC, "ub", X86vpcomu, v16i8, SchedWriteVecALU.XMM>;
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defm VPCOMUW : xopvpcom<0xED, "uw", X86vpcomu, v8i16, SchedWriteVecALU.XMM>;
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defm VPCOMUD : xopvpcom<0xEE, "ud", X86vpcomu, v4i32, SchedWriteVecALU.XMM>;
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defm VPCOMUQ : xopvpcom<0xEF, "uq", X86vpcomu, v2i64, SchedWriteVecALU.XMM>;
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multiclass xop4op<bits<8> opc, string OpcodeStr, SDNode OpNode,
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ValueType vt128, X86FoldableSchedWrite sched> {
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def rrr : IXOPi8Reg<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set VR128:$dst,
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(vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2),
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(vt128 VR128:$src3))))]>,
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XOP_4V, Sched<[sched]>;
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def rrm : IXOPi8Reg<opc, MRMSrcMemOp4, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, i128mem:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set VR128:$dst,
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(vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2),
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(vt128 (load addr:$src3)))))]>,
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XOP_4V, VEX_W, Sched<[sched.Folded, sched.ReadAfterFold, sched.ReadAfterFold]>;
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def rmr : IXOPi8Reg<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set VR128:$dst,
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(v16i8 (OpNode (vt128 VR128:$src1), (vt128 (load addr:$src2)),
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(vt128 VR128:$src3))))]>,
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XOP_4V, Sched<[sched.Folded, sched.ReadAfterFold,
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// 128mem:$src2
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ReadDefault, ReadDefault, ReadDefault, ReadDefault,
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ReadDefault,
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// VR128:$src3
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sched.ReadAfterFold]>;
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// For disassembler
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let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
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def rrr_REV : IXOPi8Reg<opc, MRMSrcRegOp4, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[]>, XOP_4V, VEX_W, Sched<[sched]>, FoldGenData<NAME#rrr>;
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}
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let ExeDomain = SSEPackedInt in {
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defm VPPERM : xop4op<0xA3, "vpperm", X86vpperm, v16i8,
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SchedWriteVarShuffle.XMM>;
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}
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// Instruction where either second or third source can be memory
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multiclass xop4op_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
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X86MemOperand x86memop, ValueType VT,
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X86FoldableSchedWrite sched> {
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def rrr : IXOPi8Reg<opc, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, RC:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set RC:$dst, (VT (or (and RC:$src3, RC:$src1),
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(X86andnp RC:$src3, RC:$src2))))]>, XOP_4V,
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Sched<[sched]>;
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// FIXME: This pattern can't match.
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def rrm : IXOPi8Reg<opc, MRMSrcMemOp4, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, x86memop:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set RC:$dst, (VT (or (and (load addr:$src3), RC:$src1),
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(X86andnp (load addr:$src3), RC:$src2))))]>,
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XOP_4V, VEX_W, Sched<[sched.Folded, sched.ReadAfterFold, sched.ReadAfterFold]>;
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def rmr : IXOPi8Reg<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, x86memop:$src2, RC:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set RC:$dst, (VT (or (and RC:$src3, RC:$src1),
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(X86andnp RC:$src3, (load addr:$src2)))))]>,
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XOP_4V, Sched<[sched.Folded, sched.ReadAfterFold,
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// x86memop:$src2
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ReadDefault, ReadDefault, ReadDefault, ReadDefault,
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ReadDefault,
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// RC::$src3
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sched.ReadAfterFold]>;
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// For disassembler
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let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
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def rrr_REV : IXOPi8Reg<opc, MRMSrcRegOp4, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, RC:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[]>, XOP_4V, VEX_W, Sched<[sched]>, FoldGenData<NAME#rrr>;
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}
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let ExeDomain = SSEPackedInt in {
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defm VPCMOV : xop4op_int<0xA2, "vpcmov", VR128, i128mem, v2i64,
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SchedWriteShuffle.XMM>;
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defm VPCMOVY : xop4op_int<0xA2, "vpcmov", VR256, i256mem, v4i64,
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SchedWriteShuffle.YMM>, VEX_L;
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}
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let Predicates = [HasXOP] in {
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def : Pat<(v16i8 (or (and VR128:$src3, VR128:$src1),
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(X86andnp VR128:$src3, VR128:$src2))),
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(VPCMOVrrr VR128:$src1, VR128:$src2, VR128:$src3)>;
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def : Pat<(v8i16 (or (and VR128:$src3, VR128:$src1),
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(X86andnp VR128:$src3, VR128:$src2))),
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(VPCMOVrrr VR128:$src1, VR128:$src2, VR128:$src3)>;
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def : Pat<(v4i32 (or (and VR128:$src3, VR128:$src1),
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(X86andnp VR128:$src3, VR128:$src2))),
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(VPCMOVrrr VR128:$src1, VR128:$src2, VR128:$src3)>;
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def : Pat<(or (and VR128:$src3, VR128:$src1),
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(X86andnp VR128:$src3, (bc_v16i8 (loadv2i64 addr:$src2)))),
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(VPCMOVrmr VR128:$src1, addr:$src2, VR128:$src3)>;
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def : Pat<(or (and VR128:$src3, VR128:$src1),
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(X86andnp VR128:$src3, (bc_v8i16 (loadv2i64 addr:$src2)))),
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(VPCMOVrmr VR128:$src1, addr:$src2, VR128:$src3)>;
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def : Pat<(or (and VR128:$src3, VR128:$src1),
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(X86andnp VR128:$src3, (bc_v4i32 (loadv2i64 addr:$src2)))),
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(VPCMOVrmr VR128:$src1, addr:$src2, VR128:$src3)>;
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def : Pat<(v32i8 (or (and VR256:$src3, VR256:$src1),
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(X86andnp VR256:$src3, VR256:$src2))),
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(VPCMOVYrrr VR256:$src1, VR256:$src2, VR256:$src3)>;
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def : Pat<(v16i16 (or (and VR256:$src3, VR256:$src1),
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(X86andnp VR256:$src3, VR256:$src2))),
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(VPCMOVYrrr VR256:$src1, VR256:$src2, VR256:$src3)>;
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def : Pat<(v8i32 (or (and VR256:$src3, VR256:$src1),
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(X86andnp VR256:$src3, VR256:$src2))),
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(VPCMOVYrrr VR256:$src1, VR256:$src2, VR256:$src3)>;
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def : Pat<(or (and VR256:$src3, VR256:$src1),
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(X86andnp VR256:$src3, (bc_v32i8 (loadv4i64 addr:$src2)))),
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(VPCMOVYrmr VR256:$src1, addr:$src2, VR256:$src3)>;
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def : Pat<(or (and VR256:$src3, VR256:$src1),
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(X86andnp VR256:$src3, (bc_v16i16 (loadv4i64 addr:$src2)))),
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(VPCMOVYrmr VR256:$src1, addr:$src2, VR256:$src3)>;
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def : Pat<(or (and VR256:$src3, VR256:$src1),
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(X86andnp VR256:$src3, (bc_v8i32 (loadv4i64 addr:$src2)))),
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(VPCMOVYrmr VR256:$src1, addr:$src2, VR256:$src3)>;
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}
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multiclass xop_vpermil2<bits<8> Opc, string OpcodeStr, RegisterClass RC,
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X86MemOperand intmemop, X86MemOperand fpmemop,
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ValueType VT, PatFrag FPLdFrag, PatFrag IntLdFrag,
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X86FoldableSchedWrite sched> {
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def rr : IXOP5<Opc, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, RC:$src3, u8imm:$src4),
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!strconcat(OpcodeStr,
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"\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
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[(set RC:$dst,
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(VT (X86vpermil2 RC:$src1, RC:$src2, RC:$src3, (i8 imm:$src4))))]>,
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Sched<[sched]>;
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def rm : IXOP5<Opc, MRMSrcMemOp4, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, intmemop:$src3, u8imm:$src4),
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!strconcat(OpcodeStr,
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"\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
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[(set RC:$dst,
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(VT (X86vpermil2 RC:$src1, RC:$src2, (IntLdFrag addr:$src3),
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(i8 imm:$src4))))]>, VEX_W,
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Sched<[sched.Folded, sched.ReadAfterFold, sched.ReadAfterFold]>;
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def mr : IXOP5<Opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, fpmemop:$src2, RC:$src3, u8imm:$src4),
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!strconcat(OpcodeStr,
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"\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
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[(set RC:$dst,
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(VT (X86vpermil2 RC:$src1, (FPLdFrag addr:$src2),
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RC:$src3, (i8 imm:$src4))))]>,
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Sched<[sched.Folded, sched.ReadAfterFold,
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// fpmemop:$src2
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ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault,
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// RC:$src3
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sched.ReadAfterFold]>;
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// For disassembler
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let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
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def rr_REV : IXOP5<Opc, MRMSrcRegOp4, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, RC:$src3, u8imm:$src4),
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!strconcat(OpcodeStr,
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"\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
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[]>, VEX_W, Sched<[sched]>, FoldGenData<NAME#rr>;
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}
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let ExeDomain = SSEPackedDouble in {
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defm VPERMIL2PD : xop_vpermil2<0x49, "vpermil2pd", VR128, i128mem, f128mem,
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v2f64, loadv2f64, loadv2i64,
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SchedWriteFVarShuffle.XMM>;
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defm VPERMIL2PDY : xop_vpermil2<0x49, "vpermil2pd", VR256, i256mem, f256mem,
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v4f64, loadv4f64, loadv4i64,
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SchedWriteFVarShuffle.YMM>, VEX_L;
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}
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let ExeDomain = SSEPackedSingle in {
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defm VPERMIL2PS : xop_vpermil2<0x48, "vpermil2ps", VR128, i128mem, f128mem,
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v4f32, loadv4f32, loadv4i32,
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SchedWriteFVarShuffle.XMM>;
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defm VPERMIL2PSY : xop_vpermil2<0x48, "vpermil2ps", VR256, i256mem, f256mem,
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v8f32, loadv8f32, loadv8i32,
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SchedWriteFVarShuffle.YMM>, VEX_L;
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}
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