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96c1e7e4f0
Lay out trellis-shaped CFGs optimally.
A trellis of the shape below:
A B
|\ /|
| \ / |
| X |
| / \ |
|/ \|
C D
would be laid out A; B->C ; D by the current layout algorithm. Now we identify
trellises and lay them out either A->C; B->D or A->D; B->C. This scales with an
increasing number of predecessors. A trellis is a a group of 2 or more
predecessor blocks that all have the same successors.
because of this we can tail duplicate to extend existing trellises.
As an example consider the following CFG:
B D F H
/ \ / \ / \ / \
A---C---E---G---Ret
Where A,C,E,G are all small (Currently 2 instructions).
The CFG preserving layout is then A,B,C,D,E,F,G,H,Ret.
The current code will copy C into B, E into D and G into F and yield the layout
A,C,B(C),E,D(E),F(G),G,H,ret
define void @straight_test(i32 %tag) {
entry:
br label %test1
test1: ; A
%tagbit1 = and i32 %tag, 1
%tagbit1eq0 = icmp eq i32 %tagbit1, 0
br i1 %tagbit1eq0, label %test2, label %optional1
optional1: ; B
call void @a()
br label %test2
test2: ; C
%tagbit2 = and i32 %tag, 2
%tagbit2eq0 = icmp eq i32 %tagbit2, 0
br i1 %tagbit2eq0, label %test3, label %optional2
optional2: ; D
call void @b()
br label %test3
test3: ; E
%tagbit3 = and i32 %tag, 4
%tagbit3eq0 = icmp eq i32 %tagbit3, 0
br i1 %tagbit3eq0, label %test4, label %optional3
optional3: ; F
call void @c()
br label %test4
test4: ; G
%tagbit4 = and i32 %tag, 8
%tagbit4eq0 = icmp eq i32 %tagbit4, 0
br i1 %tagbit4eq0, label %exit, label %optional4
optional4: ; H
call void @d()
br label %exit
exit:
ret void
}
here is the layout after D27742:
straight_test: # @straight_test
; ... Prologue elided
; BB#0: # %entry ; A (merged with test1)
; ... More prologue elided
mr 30, 3
andi. 3, 30, 1
bc 12, 1, .LBB0_2
; BB#1: # %test2 ; C
rlwinm. 3, 30, 0, 30, 30
beq 0, .LBB0_3
b .LBB0_4
.LBB0_2: # %optional1 ; B (copy of C)
bl a
nop
rlwinm. 3, 30, 0, 30, 30
bne 0, .LBB0_4
.LBB0_3: # %test3 ; E
rlwinm. 3, 30, 0, 29, 29
beq 0, .LBB0_5
b .LBB0_6
.LBB0_4: # %optional2 ; D (copy of E)
bl b
nop
rlwinm. 3, 30, 0, 29, 29
bne 0, .LBB0_6
.LBB0_5: # %test4 ; G
rlwinm. 3, 30, 0, 28, 28
beq 0, .LBB0_8
b .LBB0_7
.LBB0_6: # %optional3 ; F (copy of G)
bl c
nop
rlwinm. 3, 30, 0, 28, 28
beq 0, .LBB0_8
.LBB0_7: # %optional4 ; H
bl d
nop
.LBB0_8: # %exit ; Ret
ld 30, 96(1) # 8-byte Folded Reload
addi 1, 1, 112
ld 0, 16(1)
mtlr 0
blr
The tail-duplication has produced some benefit, but it has also produced a
trellis which is not laid out optimally. With this patch, we improve the layouts
of such trellises, and decrease the cost calculation for tail-duplication
accordingly.
This patch produces the layout A,C,E,G,B,D,F,H,Ret. This layout does have
back edges, which is a negative, but it has a bigger compensating
positive, which is that it handles the case where there are long strings
of skipped blocks much better than the original layout. Both layouts
handle runs of executed blocks equally well. Branch prediction also
improves if there is any correlation between subsequent optional blocks.
Here is the resulting concrete layout:
straight_test: # @straight_test
; BB#0: # %entry ; A (merged with test1)
mr 30, 3
andi. 3, 30, 1
bc 12, 1, .LBB0_4
; BB#1: # %test2 ; C
rlwinm. 3, 30, 0, 30, 30
bne 0, .LBB0_5
.LBB0_2: # %test3 ; E
rlwinm. 3, 30, 0, 29, 29
bne 0, .LBB0_6
.LBB0_3: # %test4 ; G
rlwinm. 3, 30, 0, 28, 28
bne 0, .LBB0_7
b .LBB0_8
.LBB0_4: # %optional1 ; B (Copy of C)
bl a
nop
rlwinm. 3, 30, 0, 30, 30
beq 0, .LBB0_2
.LBB0_5: # %optional2 ; D (Copy of E)
bl b
nop
rlwinm. 3, 30, 0, 29, 29
beq 0, .LBB0_3
.LBB0_6: # %optional3 ; F (Copy of G)
bl c
nop
rlwinm. 3, 30, 0, 28, 28
beq 0, .LBB0_8
.LBB0_7: # %optional4 ; H
bl d
nop
.LBB0_8: # %exit
Differential Revision: https://reviews.llvm.org/D28522
llvm-svn: 295223
236 lines
6.6 KiB
LLVM
236 lines
6.6 KiB
LLVM
; Disable shrink-wrapping on the first test otherwise we wouldn't
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; exerce the path for PR18136.
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; RUN: llc -mtriple=thumbv7-apple-none-macho < %s -enable-shrink-wrap=false | FileCheck %s
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; RUN: llc -mtriple=thumbv6m-apple-none-macho -disable-fp-elim < %s | FileCheck %s --check-prefix=CHECK-T1
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; RUN: llc -mtriple=thumbv7-apple-darwin-ios -disable-fp-elim < %s | FileCheck %s --check-prefix=CHECK-IOS
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; RUN: llc -mtriple=thumbv7--linux-gnueabi -disable-fp-elim < %s | FileCheck %s --check-prefix=CHECK-LINUX
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declare void @bar(i8*)
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%bigVec = type [2 x double]
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@var = global %bigVec zeroinitializer
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define void @check_simple() minsize {
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; CHECK-LABEL: check_simple:
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; CHECK: push {r3, r4, r5, r6, r7, lr}
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; CHECK-NOT: sub sp, sp,
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; ...
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; CHECK-NOT: add sp, sp,
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; CHECK: pop {r0, r1, r2, r3, r7, pc}
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; CHECK-T1-LABEL: check_simple:
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; CHECK-T1: push {r3, r4, r5, r6, r7, lr}
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; CHECK-T1: add r7, sp, #16
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; CHECK-T1-NOT: sub sp, sp,
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; ...
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; CHECK-T1-NOT: add sp, sp,
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; CHECK-T1: pop {r0, r1, r2, r3, r7, pc}
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; iOS always has a frame pointer and messing with the push affects
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; how it's set in the prologue. Make sure we get that right.
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; CHECK-IOS-LABEL: check_simple:
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; CHECK-IOS: push {r3, r4, r5, r6, r7, lr}
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; CHECK-NOT: sub sp,
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; CHECK-IOS: add r7, sp, #16
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; CHECK-NOT: sub sp,
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; ...
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; CHECK-NOT: add sp,
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; CHEC: pop {r3, r4, r5, r6, r7, pc}
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%var = alloca i8, i32 16
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call void @bar(i8* %var)
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ret void
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}
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define void @check_simple_too_big() minsize {
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; CHECK-LABEL: check_simple_too_big:
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; CHECK: push {r7, lr}
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; CHECK: sub sp,
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; ...
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; CHECK: add sp,
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; CHECK: pop {r7, pc}
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%var = alloca i8, i32 64
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call void @bar(i8* %var)
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ret void
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}
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define void @check_vfp_fold() minsize {
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; CHECK-LABEL: check_vfp_fold:
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; CHECK: push {r[[GLOBREG:[0-9]+]], lr}
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; CHECK: vpush {d6, d7, d8, d9}
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; CHECK-NOT: sub sp,
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; ...
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; CHECK-NOT: add sp,
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; CHECK: vpop {d6, d7, d8, d9}
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; CHECK: pop {r[[GLOBREG]], pc}
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; iOS uses aligned NEON stores here, which is convenient since we
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; want to make sure that works too.
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; CHECK-IOS-LABEL: check_vfp_fold:
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; CHECK-IOS: push {r4, r7, lr}
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; CHECK-IOS: sub.w r4, sp, #16
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; CHECK-IOS: bfc r4, #0, #4
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; CHECK-IOS: mov sp, r4
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; CHECK-IOS: vst1.64 {d8, d9}, [r4:128]
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; CHECK-IOS: sub sp, #16
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; ...
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; CHECK-IOS: add r4, sp, #16
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; CHECK-IOS: vld1.64 {d8, d9}, [r4:128]
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; CHECK-IOS: mov sp, r4
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; CHECK-IOS: pop {r4, r7, pc}
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%var = alloca i8, i32 16
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call void asm "", "r,~{d8},~{d9}"(i8* %var)
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call void @bar(i8* %var)
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ret void
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}
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; This function should use just enough space that the "add sp, sp, ..." could be
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; folded in except that doing so would clobber the value being returned.
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define i64 @check_no_return_clobber() minsize {
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; CHECK-LABEL: check_no_return_clobber:
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; CHECK: push {r1, r2, r3, r4, r5, r6, r7, lr}
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; CHECK-NOT: sub sp,
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; ...
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; CHECK: add sp, #24
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; CHECK: pop {r7, pc}
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; Just to keep iOS FileCheck within previous function:
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; CHECK-IOS-LABEL: check_no_return_clobber:
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%var = alloca i8, i32 20
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call void @bar(i8* %var)
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ret i64 0
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}
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define arm_aapcs_vfpcc double @check_vfp_no_return_clobber() minsize {
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; CHECK-LABEL: check_vfp_no_return_clobber:
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; CHECK: push {r[[GLOBREG:[0-9]+]], lr}
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; CHECK: vpush {d0, d1, d2, d3, d4, d5, d6, d7, d8, d9}
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; CHECK-NOT: sub sp,
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; ...
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; CHECK: add sp, #64
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; CHECK: vpop {d8, d9}
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; CHECK: pop {r[[GLOBREG]], pc}
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%var = alloca i8, i32 64
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%tmp = load %bigVec, %bigVec* @var
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call void @bar(i8* %var)
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store %bigVec %tmp, %bigVec* @var
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ret double 1.0
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}
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@dbl = global double 0.0
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; PR18136: there was a bug determining where the first eligible pop in a
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; basic-block was when the entire block was epilogue code.
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define void @test_fold_point(i1 %tst) minsize {
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; CHECK-LABEL: test_fold_point:
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; Important to check for beginning of basic block, because if it gets
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; if-converted the test is probably no longer checking what it should.
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; CHECK: %end
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; CHECK-NEXT: vpop {d7, d8}
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; CHECK-NEXT: pop {r4, pc}
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; With a guaranteed frame-pointer, we want to make sure that its offset in the
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; push block is correct, even if a few registers have been tacked onto a later
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; vpush (PR18160).
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; CHECK-IOS-LABEL: test_fold_point:
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; CHECK-IOS: push {r4, r7, lr}
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; CHECK-IOS-NEXT: add r7, sp, #4
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; CHECK-IOS-NEXT: vpush {d7, d8}
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; We want some memory so there's a stack adjustment to fold...
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%var = alloca i8, i32 8
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; We want a long-lived floating register so that a callee-saved dN is used and
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; there's both a vpop and a pop.
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%live_val = load double, double* @dbl
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br i1 %tst, label %true, label %end
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true:
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call void @bar(i8* %var)
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store double %live_val, double* @dbl
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br label %end
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end:
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; We want the epilogue to be the only thing in a basic block so that we hit
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; the correct edge-case (first inst in block is correct one to adjust).
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ret void
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}
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define void @test_varsize(...) minsize {
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; CHECK-T1-LABEL: test_varsize:
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; CHECK-T1: sub sp, #16
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; CHECK-T1: push {r5, r6, r7, lr}
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; ...
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; CHECK-T1: pop {r2, r3, r7}
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; CHECK-T1: pop {[[POP_REG:r[0-3]]]}
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; CHECK-T1: add sp, #16
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; CHECK-T1: bx [[POP_REG]]
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; CHECK-LABEL: test_varsize:
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; CHECK: sub sp, #16
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; CHECK: push {r5, r6, r7, lr}
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; ...
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; CHECK: pop.w {r2, r3, r7, lr}
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; CHECK: add sp, #16
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; CHECK: bx lr
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%var = alloca i8, i32 8
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call void @llvm.va_start(i8* %var)
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call void @bar(i8* %var)
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ret void
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}
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%"MyClass" = type { i8*, i32, i32, float, float, float, [2 x i8], i32, i32* }
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declare float @foo()
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declare void @bar3()
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declare %"MyClass"* @bar2(%"MyClass"* returned, i16*, i32, float, float, i32, i32, i1 zeroext, i1 zeroext, i32)
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define fastcc float @check_vfp_no_return_clobber2(i16* %r, i16* %chars, i32 %length, i1 zeroext %flag) minsize {
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entry:
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; CHECK-LINUX-LABEL: check_vfp_no_return_clobber2
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; CHECK-LINUX: vpush {d0, d1, d2, d3, d4, d5, d6, d7, d8}
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; CHECK-NOT: sub sp,
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; ...
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; CHECK-LINUX: add sp
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; CHECK-LINUX: vpop {d8}
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%run = alloca %"MyClass", align 4
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%call = call %"MyClass"* @bar2(%"MyClass"* %run, i16* %chars, i32 %length, float 0.000000e+00, float 0.000000e+00, i32 1, i32 1, i1 zeroext false, i1 zeroext true, i32 3)
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%call1 = call float @foo()
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%cmp = icmp eq %"MyClass"* %run, null
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br i1 %cmp, label %exit, label %if.then
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if.then: ; preds = %entry
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call void @bar3()
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br label %exit
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exit: ; preds = %if.then, %entry
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ret float %call1
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}
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declare void @use_arr(i32*)
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define void @test_fold_reuse() minsize {
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; CHECK-LABEL: test_fold_reuse:
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; CHECK: push.w {r4, r7, r8, lr}
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; CHECK: sub sp, #24
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; [...]
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; CHECK: add sp, #24
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; CHECK: pop.w {r4, r7, r8, pc}
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%arr = alloca i8, i32 24
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call void asm sideeffect "", "~{r8},~{r4}"()
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call void @bar(i8* %arr)
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ret void
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}
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declare void @llvm.va_start(i8*) nounwind
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