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7d64810efd
The benchmarking summarized in http://lists.llvm.org/pipermail/llvm-dev/2017-May/113525.html showed this is beneficial for a wide range of cores. As is to be expected, quite a few small adaptations are needed to the regressions tests, as the difference in scheduling results in: - Quite a few small instruction schedule differences. - A few changes in register allocation decisions caused by different instruction schedules. - A few changes in IfConversion decisions, due to a difference in instruction schedule and/or the estimated cost of a branch mispredict. llvm-svn: 306514
31 lines
1.4 KiB
LLVM
31 lines
1.4 KiB
LLVM
; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s
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; FIXME: Need post-ifcvt branch folding to get rid of the extra br at end of BB1.
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%struct.quad_struct = type { i32, i32, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct* }
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define fastcc i32 @CountTree(%struct.quad_struct* %tree) {
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; CHECK: cmpeq
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entry:
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br label %tailrecurse
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tailrecurse: ; preds = %bb, %entry
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%tmp6 = load %struct.quad_struct*, %struct.quad_struct** null ; <%struct.quad_struct*> [#uses=1]
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%tmp9 = load %struct.quad_struct*, %struct.quad_struct** null ; <%struct.quad_struct*> [#uses=2]
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%tmp12 = load %struct.quad_struct*, %struct.quad_struct** null ; <%struct.quad_struct*> [#uses=1]
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%tmp14 = icmp eq %struct.quad_struct* null, null ; <i1> [#uses=1]
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%tmp17 = icmp eq %struct.quad_struct* %tmp6, null ; <i1> [#uses=1]
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%tmp23 = icmp eq %struct.quad_struct* %tmp9, null ; <i1> [#uses=1]
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%tmp29 = icmp eq %struct.quad_struct* %tmp12, null ; <i1> [#uses=1]
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%bothcond = and i1 %tmp17, %tmp14 ; <i1> [#uses=1]
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%bothcond1 = and i1 %bothcond, %tmp23 ; <i1> [#uses=1]
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%bothcond2 = and i1 %bothcond1, %tmp29 ; <i1> [#uses=1]
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br i1 %bothcond2, label %return, label %bb
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bb: ; preds = %tailrecurse
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%tmp41 = tail call fastcc i32 @CountTree( %struct.quad_struct* %tmp9 ) ; <i32> [#uses=0]
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br label %tailrecurse
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return: ; preds = %tailrecurse
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ret i32 0
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}
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