Krzysztof Parzyszek ce1e95e40d Move size and alignment information of regclass to TargetRegisterInfo ... 1. RegisterClass::getSize() is split into two functions: - TargetRegisterInfo::getRegSizeInBits(const TargetRegisterClass &RC) const; - TargetRegisterInfo::getSpillSize(const TargetRegisterClass &RC) const; 2. RegisterClass::getAlignment() is replaced by: - TargetRegisterInfo::getSpillAlignment(const TargetRegisterClass &RC) const; This will allow making those values depend on subtarget features in the future. Differential Revision: https://reviews.llvm.org/D31783 llvm-svn: 301221		2017-04-24 18:55:33 +00:00
..
AsmParser	[Arch64AsmParser] better diagnostic for isb	2017-04-24 08:22:20 +00:00
Disassembler
InstPrinter	AArch64: lower "fence singlethread" to a pure compiler barrier.	2017-04-20 21:57:45 +00:00
MCTargetDesc	AArch64: lower "fence singlethread" to a pure compiler barrier.	2017-04-20 21:57:45 +00:00
TargetInfo
Utils
AArch64.h	[globalisel][tablegen] Move <Target>InstructionSelector declarations to anonymous namespaces	2017-04-06 09:49:34 +00:00
AArch64.td	[AArch64] Crypto requires FP.	2017-04-05 10:44:38 +00:00
AArch64A53Fix835769.cpp
AArch64A57FPLoadBalancing.cpp
AArch64AddressTypePromotion.cpp
AArch64AdvSIMDScalarPass.cpp
AArch64AsmPrinter.cpp
AArch64CallingConvention.h
AArch64CallingConvention.td
AArch64CallLowering.cpp
AArch64CallLowering.h
AArch64CleanupLocalDynamicTLSPass.cpp
AArch64CollectLOH.cpp
AArch64ConditionalCompares.cpp
AArch64ConditionOptimizer.cpp
AArch64DeadRegisterDefinitionsPass.cpp
AArch64ExpandPseudoInsts.cpp	AArch64: lower "fence singlethread" to a pure compiler barrier.	2017-04-20 21:57:45 +00:00
AArch64FastISel.cpp	[AArch64][Fuchsia] Allow -mcmodel=kernel for --target=aarch64-fuchsia	2017-04-04 19:51:53 +00:00
AArch64FrameLowering.cpp	Move size and alignment information of regclass to TargetRegisterInfo	2017-04-24 18:55:33 +00:00
AArch64FrameLowering.h
AArch64GenRegisterBankInfo.def
AArch64InstrAtomics.td	AArch64: lower "fence singlethread" to a pure compiler barrier.	2017-04-20 21:57:45 +00:00
AArch64InstrFormats.td	[globalisel][tablegen] Revise API for ComplexPattern operands to improve flexibility.	2017-04-22 15:11:04 +00:00
AArch64InstrInfo.cpp	Move size and alignment information of regclass to TargetRegisterInfo	2017-04-24 18:55:33 +00:00
AArch64InstrInfo.h	Re-commit r301040 "X86: Don't emit zero-byte functions on Windows"	2017-04-21 21:48:41 +00:00
AArch64InstrInfo.td	[AArch64] Fix handling of zero immediate in fmov instructions	2017-04-20 10:13:54 +00:00
AArch64InstructionSelector.cpp	[globalisel][tablegen] Revise API for ComplexPattern operands to improve flexibility.	2017-04-22 15:11:04 +00:00
AArch64ISelDAGToDAG.cpp	Revert "[APInt] Fix a few places that use APInt::getRawData to operate within the normal API."	2017-04-23 12:15:30 +00:00
AArch64ISelLowering.cpp	[AArch64] Improve code generation for logical instructions taking	2017-04-21 18:53:12 +00:00
AArch64ISelLowering.h	[AArch64] Improve code generation for logical instructions taking	2017-04-21 18:53:12 +00:00
AArch64LegalizerInfo.cpp
AArch64LegalizerInfo.h
AArch64LoadStoreOptimizer.cpp
AArch64MachineFunctionInfo.h
AArch64MacroFusion.cpp	[AArch64] Simplify MacroFusion	2017-04-11 19:13:11 +00:00
AArch64MacroFusion.h
AArch64MCInstLower.cpp
AArch64MCInstLower.h
AArch64PBQPRegAlloc.cpp
AArch64PBQPRegAlloc.h
AArch64PerfectShuffle.h
AArch64PromoteConstant.cpp
AArch64RedundantCopyElimination.cpp
AArch64RegisterBankInfo.cpp	[GlobalISel] Support vector-of-pointers in LLT	2017-04-19 07:23:57 +00:00
AArch64RegisterBankInfo.h
AArch64RegisterBanks.td
AArch64RegisterInfo.cpp
AArch64RegisterInfo.h
AArch64RegisterInfo.td
AArch64SchedA53.td
AArch64SchedA57.td
AArch64SchedA57WriteRes.td
AArch64SchedCyclone.td
AArch64SchedFalkor.td	[AArch64][Falkor] Fix number of microops for WriteSTIdx missed in r300892.	2017-04-21 13:37:01 +00:00
AArch64SchedFalkorDetails.td	[AArch64][Falkor] Refine modeling of store-release exclusive instructions.	2017-04-21 14:58:32 +00:00
AArch64SchedFalkorWriteRes.td	[AArch64][Falkor] Refine modeling of store-release exclusive instructions.	2017-04-21 14:58:32 +00:00
AArch64SchedKryo.td
AArch64SchedKryoDetails.td
AArch64SchedM1.td
AArch64SchedThunderX2T99.td
AArch64SchedThunderX.td
AArch64Schedule.td
AArch64SelectionDAGInfo.cpp
AArch64SelectionDAGInfo.h
AArch64StorePairSuppress.cpp
AArch64Subtarget.cpp	AArch64: put nonlazybind special handling behind a flag for now.	2017-04-17 18:18:47 +00:00
AArch64Subtarget.h	AArch64: support nonlazybind	2017-04-17 17:27:56 +00:00
AArch64SystemOperands.td
AArch64TargetMachine.cpp	[globalisel][tablegen] Move <Target>InstructionSelector declarations to anonymous namespaces	2017-04-06 09:49:34 +00:00
AArch64TargetMachine.h	[globalisel][tablegen] Move <Target>InstructionSelector declarations to anonymous namespaces	2017-04-06 09:49:34 +00:00
AArch64TargetObjectFile.cpp
AArch64TargetObjectFile.h
AArch64TargetTransformInfo.cpp	[SystemZ] TargetTransformInfo cost functions implemented.	2017-04-12 11:49:08 +00:00
AArch64TargetTransformInfo.h	[SystemZ] TargetTransformInfo cost functions implemented.	2017-04-12 11:49:08 +00:00
AArch64VectorByElementOpt.cpp
CMakeLists.txt
LLVMBuild.txt