mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-22 18:54:02 +01:00
d1818e7c07
Summary: The illegal instruction 0x00 0x00 is being wrongly decoded as c.addi4spn with 0 immediate. The invalid instruction 0x01 0x61 is being wrongly decoded as c.addi16sp with 0 immediate. This bug was uncovered by a LLVM MC Disassembler Protocol Buffer Fuzzer for the RISC-V assembly language. Reviewers: asb Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, asb Differential Revision: https://reviews.llvm.org/D51815 llvm-svn: 342159
708 lines
25 KiB
TableGen
708 lines
25 KiB
TableGen
//===- RISCVInstrInfoC.td - Compressed RISCV instructions -*- tblgen-*-----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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include "RISCVInstrFormatsC.td"
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//===----------------------------------------------------------------------===//
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// Operand definitions.
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//===----------------------------------------------------------------------===//
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def UImmLog2XLenNonZeroAsmOperand : AsmOperandClass {
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let Name = "UImmLog2XLenNonZero";
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let RenderMethod = "addImmOperands";
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let DiagnosticType = "InvalidUImmLog2XLenNonZero";
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}
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def uimmlog2xlennonzero : Operand<XLenVT>, ImmLeaf<XLenVT, [{
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if (Subtarget->is64Bit())
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return isUInt<6>(Imm) && (Imm != 0);
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return isUInt<5>(Imm) && (Imm != 0);
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}]> {
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let ParserMatchClass = UImmLog2XLenNonZeroAsmOperand;
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// TODO: should ensure invalid shamt is rejected when decoding.
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let DecoderMethod = "decodeUImmOperand<6>";
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let MCOperandPredicate = [{
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int64_t Imm;
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if (!MCOp.evaluateAsConstantImm(Imm))
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return false;
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if (STI.getTargetTriple().isArch64Bit())
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return isUInt<6>(Imm) && (Imm != 0);
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return isUInt<5>(Imm) && (Imm != 0);
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}];
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}
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def simm6 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isInt<6>(Imm);}]> {
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let ParserMatchClass = SImmAsmOperand<6>;
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let EncoderMethod = "getImmOpValue";
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let DecoderMethod = "decodeSImmOperand<6>";
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let MCOperandPredicate = [{
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int64_t Imm;
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if (MCOp.evaluateAsConstantImm(Imm))
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return isInt<6>(Imm);
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return MCOp.isBareSymbolRef();
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}];
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}
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def simm6nonzero : Operand<XLenVT>,
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ImmLeaf<XLenVT, [{return (Imm != 0) && isInt<6>(Imm);}]> {
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let ParserMatchClass = SImmAsmOperand<6, "NonZero">;
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let EncoderMethod = "getImmOpValue";
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let DecoderMethod = "decodeSImmOperand<6>";
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let MCOperandPredicate = [{
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int64_t Imm;
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if (MCOp.evaluateAsConstantImm(Imm))
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return (Imm != 0) && isInt<6>(Imm);
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return MCOp.isBareSymbolRef();
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}];
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}
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def CLUIImmAsmOperand : AsmOperandClass {
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let Name = "CLUIImm";
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let RenderMethod = "addImmOperands";
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let DiagnosticType = !strconcat("Invalid", Name);
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}
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// c_lui_imm checks the immediate range is in [1, 31] or [0xfffe0, 0xfffff].
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// The RISC-V ISA describes the constraint as [1, 63], with that value being
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// loaded in to bits 17-12 of the destination register and sign extended from
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// bit 17. Therefore, this 6-bit immediate can represent values in the ranges
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// [1, 31] and [0xfffe0, 0xfffff].
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def c_lui_imm : Operand<XLenVT>,
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ImmLeaf<XLenVT, [{return (Imm != 0) &&
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(isUInt<5>(Imm) ||
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(Imm >= 0xfffe0 && Imm <= 0xfffff));}]> {
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let ParserMatchClass = CLUIImmAsmOperand;
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let EncoderMethod = "getImmOpValue";
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let DecoderMethod = "decodeCLUIImmOperand";
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let MCOperandPredicate = [{
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int64_t Imm;
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if (MCOp.evaluateAsConstantImm(Imm))
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return (Imm != 0) && (isUInt<5>(Imm) ||
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(Imm >= 0xfffe0 && Imm <= 0xfffff));
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return MCOp.isBareSymbolRef();
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}];
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}
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// A 7-bit unsigned immediate where the least significant two bits are zero.
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def uimm7_lsb00 : Operand<XLenVT>,
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ImmLeaf<XLenVT, [{return isShiftedUInt<5, 2>(Imm);}]> {
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let ParserMatchClass = UImmAsmOperand<7, "Lsb00">;
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let EncoderMethod = "getImmOpValue";
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let DecoderMethod = "decodeUImmOperand<7>";
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let MCOperandPredicate = [{
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int64_t Imm;
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if (!MCOp.evaluateAsConstantImm(Imm))
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return false;
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return isShiftedUInt<5, 2>(Imm);
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}];
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}
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// A 8-bit unsigned immediate where the least significant two bits are zero.
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def uimm8_lsb00 : Operand<XLenVT>,
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ImmLeaf<XLenVT, [{return isShiftedUInt<6, 2>(Imm);}]> {
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let ParserMatchClass = UImmAsmOperand<8, "Lsb00">;
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let EncoderMethod = "getImmOpValue";
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let DecoderMethod = "decodeUImmOperand<8>";
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let MCOperandPredicate = [{
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int64_t Imm;
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if (!MCOp.evaluateAsConstantImm(Imm))
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return false;
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return isShiftedUInt<6, 2>(Imm);
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}];
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}
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// A 8-bit unsigned immediate where the least significant three bits are zero.
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def uimm8_lsb000 : Operand<XLenVT>,
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ImmLeaf<XLenVT, [{return isShiftedUInt<5, 3>(Imm);}]> {
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let ParserMatchClass = UImmAsmOperand<8, "Lsb000">;
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let EncoderMethod = "getImmOpValue";
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let DecoderMethod = "decodeUImmOperand<8>";
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let MCOperandPredicate = [{
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int64_t Imm;
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if (!MCOp.evaluateAsConstantImm(Imm))
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return false;
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return isShiftedUInt<5, 3>(Imm);
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}];
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}
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// A 9-bit signed immediate where the least significant bit is zero.
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def simm9_lsb0 : Operand<OtherVT> {
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let ParserMatchClass = SImmAsmOperand<9, "Lsb0">;
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let EncoderMethod = "getImmOpValueAsr1";
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let DecoderMethod = "decodeSImmOperandAndLsl1<9>";
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let MCOperandPredicate = [{
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int64_t Imm;
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if (MCOp.evaluateAsConstantImm(Imm))
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return isShiftedInt<8, 1>(Imm);
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return MCOp.isBareSymbolRef();
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}];
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}
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// A 9-bit unsigned immediate where the least significant three bits are zero.
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def uimm9_lsb000 : Operand<XLenVT>,
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ImmLeaf<XLenVT, [{return isShiftedUInt<6, 3>(Imm);}]> {
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let ParserMatchClass = UImmAsmOperand<9, "Lsb000">;
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let EncoderMethod = "getImmOpValue";
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let DecoderMethod = "decodeUImmOperand<9>";
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let MCOperandPredicate = [{
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int64_t Imm;
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if (!MCOp.evaluateAsConstantImm(Imm))
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return false;
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return isShiftedUInt<6, 3>(Imm);
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}];
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}
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// A 10-bit unsigned immediate where the least significant two bits are zero
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// and the immediate can't be zero.
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def uimm10_lsb00nonzero : Operand<XLenVT>,
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ImmLeaf<XLenVT,
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[{return isShiftedUInt<8, 2>(Imm) && (Imm != 0);}]> {
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let ParserMatchClass = UImmAsmOperand<10, "Lsb00NonZero">;
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let EncoderMethod = "getImmOpValue";
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let DecoderMethod = "decodeUImmNonZeroOperand<10>";
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let MCOperandPredicate = [{
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int64_t Imm;
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if (!MCOp.evaluateAsConstantImm(Imm))
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return false;
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return isShiftedUInt<8, 2>(Imm) && (Imm != 0);
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}];
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}
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// A 10-bit signed immediate where the least significant four bits are zero.
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def simm10_lsb0000nonzero : Operand<XLenVT>,
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ImmLeaf<XLenVT,
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[{return (Imm != 0) && isShiftedInt<6, 4>(Imm);}]> {
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let ParserMatchClass = SImmAsmOperand<10, "Lsb0000NonZero">;
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let EncoderMethod = "getImmOpValue";
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let DecoderMethod = "decodeSImmNonZeroOperand<10>";
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let MCOperandPredicate = [{
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int64_t Imm;
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if (!MCOp.evaluateAsConstantImm(Imm))
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return false;
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return isShiftedInt<6, 4>(Imm) && (Imm != 0);
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}];
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}
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// A 12-bit signed immediate where the least significant bit is zero.
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def simm12_lsb0 : Operand<XLenVT> {
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let ParserMatchClass = SImmAsmOperand<12, "Lsb0">;
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let EncoderMethod = "getImmOpValueAsr1";
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let DecoderMethod = "decodeSImmOperandAndLsl1<12>";
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let MCOperandPredicate = [{
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int64_t Imm;
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if (MCOp.evaluateAsConstantImm(Imm))
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return isShiftedInt<11, 1>(Imm);
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return MCOp.isBareSymbolRef();
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}];
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}
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//===----------------------------------------------------------------------===//
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// Instruction Class Templates
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//===----------------------------------------------------------------------===//
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let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
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class CStackLoad<bits<3> funct3, string OpcodeStr,
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RegisterClass cls, DAGOperand opnd>
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: RVInst16CI<funct3, 0b10, (outs cls:$rd), (ins SP:$rs1, opnd:$imm),
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OpcodeStr, "$rd, ${imm}(${rs1})">;
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let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
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class CStackStore<bits<3> funct3, string OpcodeStr,
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RegisterClass cls, DAGOperand opnd>
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: RVInst16CSS<funct3, 0b10, (outs), (ins cls:$rs2, SP:$rs1, opnd:$imm),
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OpcodeStr, "$rs2, ${imm}(${rs1})">;
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let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
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class CLoad_ri<bits<3> funct3, string OpcodeStr,
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RegisterClass cls, DAGOperand opnd>
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: RVInst16CL<funct3, 0b00, (outs cls:$rd), (ins GPRC:$rs1, opnd:$imm),
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OpcodeStr, "$rd, ${imm}(${rs1})">;
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let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
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class CStore_rri<bits<3> funct3, string OpcodeStr,
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RegisterClass cls, DAGOperand opnd>
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: RVInst16CS<funct3, 0b00, (outs), (ins cls:$rs2, GPRC:$rs1, opnd:$imm),
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OpcodeStr, "$rs2, ${imm}(${rs1})">;
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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class Bcz<bits<3> funct3, string OpcodeStr, PatFrag CondOp,
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RegisterClass cls>
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: RVInst16CB<funct3, 0b01, (outs), (ins cls:$rs1, simm9_lsb0:$imm),
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OpcodeStr, "$rs1, $imm"> {
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let isBranch = 1;
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let isTerminator = 1;
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let Inst{12} = imm{7};
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let Inst{11-10} = imm{3-2};
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let Inst{6-5} = imm{6-5};
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let Inst{4-3} = imm{1-0};
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let Inst{2} = imm{4};
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}
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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class Shift_right<bits<2> funct2, string OpcodeStr, RegisterClass cls,
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Operand ImmOpnd>
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: RVInst16CB<0b100, 0b01, (outs cls:$rs1_wb), (ins cls:$rs1, ImmOpnd:$imm),
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OpcodeStr, "$rs1, $imm"> {
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let Constraints = "$rs1 = $rs1_wb";
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let Inst{12} = imm{5};
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let Inst{11-10} = funct2;
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let Inst{6-2} = imm{4-0};
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}
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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class CS_ALU<bits<2> funct2, string OpcodeStr, RegisterClass cls,
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bit RV64only>
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: RVInst16CS<0b100, 0b01, (outs cls:$rd_wb), (ins cls:$rd, cls:$rs2),
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OpcodeStr, "$rd, $rs2"> {
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bits<3> rd;
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let Constraints = "$rd = $rd_wb";
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let Inst{12} = RV64only;
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let Inst{11-10} = 0b11;
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let Inst{9-7} = rd;
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let Inst{6-5} = funct2;
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}
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
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let Predicates = [HasStdExtC] in {
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Uses = [X2] in
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def C_ADDI4SPN : RVInst16CIW<0b000, 0b00, (outs GPRC:$rd),
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(ins SP:$rs1, uimm10_lsb00nonzero:$imm),
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"c.addi4spn", "$rd, $rs1, $imm"> {
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bits<5> rs1;
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let Inst{12-11} = imm{5-4};
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let Inst{10-7} = imm{9-6};
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let Inst{6} = imm{2};
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let Inst{5} = imm{3};
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}
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let Predicates = [HasStdExtC, HasStdExtD] in
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def C_FLD : CLoad_ri<0b001, "c.fld", FPR64C, uimm8_lsb000> {
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bits<8> imm;
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let Inst{12-10} = imm{5-3};
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let Inst{6-5} = imm{7-6};
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}
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def C_LW : CLoad_ri<0b010, "c.lw", GPRC, uimm7_lsb00> {
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bits<7> imm;
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let Inst{12-10} = imm{5-3};
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let Inst{6} = imm{2};
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let Inst{5} = imm{6};
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}
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let DecoderNamespace = "RISCV32Only_",
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Predicates = [HasStdExtC, HasStdExtF, IsRV32] in
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def C_FLW : CLoad_ri<0b011, "c.flw", FPR32C, uimm7_lsb00> {
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bits<7> imm;
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let Inst{12-10} = imm{5-3};
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let Inst{6} = imm{2};
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let Inst{5} = imm{6};
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}
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let Predicates = [HasStdExtC, IsRV64] in
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def C_LD : CLoad_ri<0b011, "c.ld", GPRC, uimm8_lsb000> {
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bits<8> imm;
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let Inst{12-10} = imm{5-3};
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let Inst{6-5} = imm{7-6};
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}
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let Predicates = [HasStdExtC, HasStdExtD] in
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def C_FSD : CStore_rri<0b101, "c.fsd", FPR64C, uimm8_lsb000> {
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bits<8> imm;
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let Inst{12-10} = imm{5-3};
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let Inst{6-5} = imm{7-6};
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}
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def C_SW : CStore_rri<0b110, "c.sw", GPRC, uimm7_lsb00> {
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bits<7> imm;
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let Inst{12-10} = imm{5-3};
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let Inst{6} = imm{2};
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let Inst{5} = imm{6};
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}
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let DecoderNamespace = "RISCV32Only_",
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Predicates = [HasStdExtC, HasStdExtF, IsRV32] in
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def C_FSW : CStore_rri<0b111, "c.fsw", FPR32C, uimm7_lsb00> {
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bits<7> imm;
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let Inst{12-10} = imm{5-3};
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let Inst{6} = imm{2};
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let Inst{5} = imm{6};
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}
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let Predicates = [HasStdExtC, IsRV64] in
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def C_SD : CStore_rri<0b111, "c.sd", GPRC, uimm8_lsb000> {
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bits<8> imm;
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let Inst{12-10} = imm{5-3};
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let Inst{6-5} = imm{7-6};
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}
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let rd = 0, imm = 0, hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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def C_NOP : RVInst16CI<0b000, 0b01, (outs), (ins), "c.nop", "">;
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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def C_ADDI : RVInst16CI<0b000, 0b01, (outs GPRNoX0:$rd_wb),
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(ins GPRNoX0:$rd, simm6nonzero:$imm),
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"c.addi", "$rd, $imm"> {
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let Constraints = "$rd = $rd_wb";
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let Inst{6-2} = imm{4-0};
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}
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCall = 1,
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DecoderNamespace = "RISCV32Only_", Defs = [X1],
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Predicates = [HasStdExtC, IsRV32] in
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def C_JAL : RVInst16CJ<0b001, 0b01, (outs), (ins simm12_lsb0:$offset),
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"c.jal", "$offset">;
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0,
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Predicates = [HasStdExtC, IsRV64] in
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def C_ADDIW : RVInst16CI<0b001, 0b01, (outs GPRNoX0:$rd_wb),
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(ins GPRNoX0:$rd, simm6:$imm),
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"c.addiw", "$rd, $imm"> {
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let Constraints = "$rd = $rd_wb";
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let Inst{6-2} = imm{4-0};
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}
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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def C_LI : RVInst16CI<0b010, 0b01, (outs GPRNoX0:$rd), (ins simm6:$imm),
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"c.li", "$rd, $imm"> {
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let Inst{6-2} = imm{4-0};
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}
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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def C_ADDI16SP : RVInst16CI<0b011, 0b01, (outs SP:$rd_wb),
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(ins SP:$rd, simm10_lsb0000nonzero:$imm),
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"c.addi16sp", "$rd, $imm"> {
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let Constraints = "$rd = $rd_wb";
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let Inst{12} = imm{9};
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let Inst{11-7} = 2;
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let Inst{6} = imm{4};
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let Inst{5} = imm{6};
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let Inst{4-3} = imm{8-7};
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let Inst{2} = imm{5};
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}
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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def C_LUI : RVInst16CI<0b011, 0b01, (outs GPRNoX0X2:$rd),
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(ins c_lui_imm:$imm),
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"c.lui", "$rd, $imm"> {
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let Inst{6-2} = imm{4-0};
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}
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def C_SRLI : Shift_right<0b00, "c.srli", GPRC, uimmlog2xlennonzero>;
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def C_SRAI : Shift_right<0b01, "c.srai", GPRC, uimmlog2xlennonzero>;
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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def C_ANDI : RVInst16CB<0b100, 0b01, (outs GPRC:$rs1_wb), (ins GPRC:$rs1, simm6:$imm),
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"c.andi", "$rs1, $imm"> {
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let Constraints = "$rs1 = $rs1_wb";
|
|
let Inst{12} = imm{5};
|
|
let Inst{11-10} = 0b10;
|
|
let Inst{6-2} = imm{4-0};
|
|
}
|
|
|
|
def C_SUB : CS_ALU<0b00, "c.sub", GPRC, 0>;
|
|
def C_XOR : CS_ALU<0b01, "c.xor", GPRC, 0>;
|
|
def C_OR : CS_ALU<0b10, "c.or" , GPRC, 0>;
|
|
def C_AND : CS_ALU<0b11, "c.and", GPRC, 0>;
|
|
|
|
let Predicates = [HasStdExtC, IsRV64] in {
|
|
def C_SUBW : CS_ALU<0b00, "c.subw", GPRC, 1>;
|
|
def C_ADDW : CS_ALU<0b01, "c.addw", GPRC, 1>;
|
|
}
|
|
|
|
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
|
|
def C_J : RVInst16CJ<0b101, 0b01, (outs), (ins simm12_lsb0:$offset),
|
|
"c.j", "$offset"> {
|
|
let isBranch = 1;
|
|
let isTerminator=1;
|
|
let isBarrier=1;
|
|
}
|
|
|
|
def C_BEQZ : Bcz<0b110, "c.beqz", seteq, GPRC>;
|
|
def C_BNEZ : Bcz<0b111, "c.bnez", setne, GPRC>;
|
|
|
|
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
|
|
def C_SLLI : RVInst16CI<0b000, 0b10, (outs GPRNoX0:$rd_wb),
|
|
(ins GPRNoX0:$rd, uimmlog2xlennonzero:$imm),
|
|
"c.slli" ,"$rd, $imm"> {
|
|
let Constraints = "$rd = $rd_wb";
|
|
let Inst{6-2} = imm{4-0};
|
|
}
|
|
|
|
let Predicates = [HasStdExtC, HasStdExtD] in
|
|
def C_FLDSP : CStackLoad<0b001, "c.fldsp", FPR64, uimm9_lsb000> {
|
|
let Inst{6-5} = imm{4-3};
|
|
let Inst{4-2} = imm{8-6};
|
|
}
|
|
|
|
def C_LWSP : CStackLoad<0b010, "c.lwsp", GPRNoX0, uimm8_lsb00> {
|
|
let Inst{6-4} = imm{4-2};
|
|
let Inst{3-2} = imm{7-6};
|
|
}
|
|
|
|
let DecoderNamespace = "RISCV32Only_",
|
|
Predicates = [HasStdExtC, HasStdExtF, IsRV32] in
|
|
def C_FLWSP : CStackLoad<0b011, "c.flwsp", FPR32, uimm8_lsb00> {
|
|
let Inst{6-4} = imm{4-2};
|
|
let Inst{3-2} = imm{7-6};
|
|
}
|
|
|
|
let Predicates = [HasStdExtC, IsRV64] in
|
|
def C_LDSP : CStackLoad<0b011, "c.ldsp", GPRNoX0, uimm9_lsb000> {
|
|
let Inst{6-5} = imm{4-3};
|
|
let Inst{4-2} = imm{8-6};
|
|
}
|
|
|
|
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
|
|
def C_JR : RVInst16CR<0b1000, 0b10, (outs), (ins GPRNoX0:$rs1),
|
|
"c.jr", "$rs1"> {
|
|
let isBranch = 1;
|
|
let isBarrier = 1;
|
|
let isTerminator = 1;
|
|
let isIndirectBranch = 1;
|
|
let rs2 = 0;
|
|
}
|
|
|
|
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
|
|
def C_MV : RVInst16CR<0b1000, 0b10, (outs GPRNoX0:$rs1), (ins GPRNoX0:$rs2),
|
|
"c.mv", "$rs1, $rs2">;
|
|
|
|
let rs1 = 0, rs2 = 0, hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
|
|
def C_EBREAK : RVInst16CR<0b1001, 0b10, (outs), (ins), "c.ebreak", "">;
|
|
|
|
let hasSideEffects = 0, mayLoad = 0, mayStore = 0,
|
|
isCall=1, Defs=[X1], rs2 = 0 in
|
|
def C_JALR : RVInst16CR<0b1001, 0b10, (outs), (ins GPRNoX0:$rs1),
|
|
"c.jalr", "$rs1">;
|
|
|
|
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
|
|
def C_ADD : RVInst16CR<0b1001, 0b10, (outs GPRNoX0:$rs1_wb),
|
|
(ins GPRNoX0:$rs1, GPRNoX0:$rs2),
|
|
"c.add", "$rs1, $rs2"> {
|
|
let Constraints = "$rs1 = $rs1_wb";
|
|
}
|
|
|
|
let Predicates = [HasStdExtC, HasStdExtD] in
|
|
def C_FSDSP : CStackStore<0b101, "c.fsdsp", FPR64, uimm9_lsb000> {
|
|
let Inst{12-10} = imm{5-3};
|
|
let Inst{9-7} = imm{8-6};
|
|
}
|
|
|
|
def C_SWSP : CStackStore<0b110, "c.swsp", GPR, uimm8_lsb00> {
|
|
let Inst{12-9} = imm{5-2};
|
|
let Inst{8-7} = imm{7-6};
|
|
}
|
|
|
|
let DecoderNamespace = "RISCV32Only_",
|
|
Predicates = [HasStdExtC, HasStdExtF, IsRV32] in
|
|
def C_FSWSP : CStackStore<0b111, "c.fswsp", FPR32, uimm8_lsb00> {
|
|
let Inst{12-9} = imm{5-2};
|
|
let Inst{8-7} = imm{7-6};
|
|
}
|
|
|
|
let Predicates = [HasStdExtC, IsRV64] in
|
|
def C_SDSP : CStackStore<0b111, "c.sdsp", GPR, uimm9_lsb000> {
|
|
let Inst{12-10} = imm{5-3};
|
|
let Inst{9-7} = imm{8-6};
|
|
}
|
|
|
|
} // Predicates = [HasStdExtC]
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Compress Instruction tablegen backend.
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
class CompressPat<dag input, dag output> {
|
|
dag Input = input;
|
|
dag Output = output;
|
|
list<Predicate> Predicates = [];
|
|
}
|
|
|
|
// Patterns are defined in the same order the compressed instructions appear
|
|
// on page 82 of the ISA manual.
|
|
|
|
// Quadrant 0
|
|
let Predicates = [HasStdExtC] in {
|
|
def : CompressPat<(ADDI GPRC:$rd, SP:$rs1, uimm10_lsb00nonzero:$imm),
|
|
(C_ADDI4SPN GPRC:$rd, SP:$rs1, uimm10_lsb00nonzero:$imm)>;
|
|
} // Predicates = [HasStdExtC]
|
|
|
|
let Predicates = [HasStdExtC, HasStdExtD] in {
|
|
def : CompressPat<(FLD FPR64C:$rd, GPRC:$rs1, uimm8_lsb000:$imm),
|
|
(C_FLD FPR64C:$rd, GPRC:$rs1, uimm8_lsb000:$imm)>;
|
|
} // Predicates = [HasStdExtC, HasStdExtD]
|
|
|
|
let Predicates = [HasStdExtC] in {
|
|
def : CompressPat<(LW GPRC:$rd, GPRC:$rs1, uimm7_lsb00:$imm),
|
|
(C_LW GPRC:$rd, GPRC:$rs1, uimm7_lsb00:$imm)>;
|
|
} // Predicates = [HasStdExtC]
|
|
|
|
let Predicates = [HasStdExtC, HasStdExtF, IsRV32] in {
|
|
def : CompressPat<(FLW FPR32C:$rd, GPRC:$rs1, uimm7_lsb00:$imm),
|
|
(C_FLW FPR32C:$rd, GPRC:$rs1, uimm7_lsb00:$imm)>;
|
|
} // Predicates = [HasStdExtC, HasStdExtF, IsRV32]
|
|
|
|
let Predicates = [HasStdExtC, IsRV64] in {
|
|
def : CompressPat<(LD GPRC:$rd, GPRC:$rs1, uimm8_lsb000:$imm),
|
|
(C_LD GPRC:$rd, GPRC:$rs1, uimm8_lsb000:$imm)>;
|
|
} // Predicates = [HasStdExtC, IsRV64]
|
|
|
|
let Predicates = [HasStdExtC, HasStdExtD] in {
|
|
def : CompressPat<(FSD FPR64C:$rs2, GPRC:$rs1, uimm8_lsb000:$imm),
|
|
(C_FSD FPR64C:$rs2, GPRC:$rs1, uimm8_lsb000:$imm)>;
|
|
} // Predicates = [HasStdExtC, HasStdExtD]
|
|
|
|
let Predicates = [HasStdExtC] in {
|
|
def : CompressPat<(SW GPRC:$rs2, GPRC:$rs1, uimm7_lsb00:$imm),
|
|
(C_SW GPRC:$rs2, GPRC:$rs1, uimm7_lsb00:$imm)>;
|
|
} // Predicates = [HasStdExtC]
|
|
|
|
let Predicates = [HasStdExtC, HasStdExtF, IsRV32] in {
|
|
def : CompressPat<(FSW FPR32C:$rs2, GPRC:$rs1,uimm7_lsb00:$imm),
|
|
(C_FSW FPR32C:$rs2, GPRC:$rs1, uimm7_lsb00:$imm)>;
|
|
} // Predicate = [HasStdExtC, HasStdExtF, IsRV32]
|
|
|
|
let Predicates = [HasStdExtC, IsRV64] in {
|
|
def : CompressPat<(SD GPRC:$rs2, GPRC:$rs1, uimm8_lsb000:$imm),
|
|
(C_SD GPRC:$rs2, GPRC:$rs1, uimm8_lsb000:$imm)>;
|
|
} // Predicates = [HasStdExtC, IsRV64]
|
|
|
|
// Quadrant 1
|
|
let Predicates = [HasStdExtC] in {
|
|
def : CompressPat<(ADDI X0, X0, 0), (C_NOP)>;
|
|
def : CompressPat<(ADDI GPRNoX0:$rs1, GPRNoX0:$rs1, simm6nonzero:$imm),
|
|
(C_ADDI GPRNoX0:$rs1, simm6nonzero:$imm)>;
|
|
} // Predicates = [HasStdExtC]
|
|
|
|
let Predicates = [HasStdExtC, IsRV32] in {
|
|
def : CompressPat<(JAL X1, simm12_lsb0:$offset),
|
|
(C_JAL simm12_lsb0:$offset)>;
|
|
} // Predicates = [HasStdExtC, IsRV32]
|
|
|
|
let Predicates = [HasStdExtC, IsRV64] in {
|
|
def : CompressPat<(ADDIW GPRNoX0:$rs1, GPRNoX0:$rs1, simm6:$imm),
|
|
(C_ADDIW GPRNoX0:$rs1, simm6:$imm)>;
|
|
} // Predicates = [HasStdExtC, IsRV64]
|
|
|
|
let Predicates = [HasStdExtC] in {
|
|
def : CompressPat<(ADDI GPRNoX0:$rd, X0, simm6:$imm),
|
|
(C_LI GPRNoX0:$rd, simm6:$imm)>;
|
|
def : CompressPat<(ADDI X2, X2, simm10_lsb0000nonzero:$imm),
|
|
(C_ADDI16SP X2, simm10_lsb0000nonzero:$imm)>;
|
|
def : CompressPat<(LUI GPRNoX0X2:$rd, c_lui_imm:$imm),
|
|
(C_LUI GPRNoX0X2:$rd, c_lui_imm:$imm)>;
|
|
def : CompressPat<(SRLI GPRC:$rs1, GPRC:$rs1, uimmlog2xlennonzero:$imm),
|
|
(C_SRLI GPRC:$rs1, uimmlog2xlennonzero:$imm)>;
|
|
def : CompressPat<(SRAI GPRC:$rs1, GPRC:$rs1, uimmlog2xlennonzero:$imm),
|
|
(C_SRAI GPRC:$rs1, uimmlog2xlennonzero:$imm)>;
|
|
def : CompressPat<(ANDI GPRC:$rs1, GPRC:$rs1, simm6:$imm),
|
|
(C_ANDI GPRC:$rs1, simm6:$imm)>;
|
|
def : CompressPat<(SUB GPRC:$rs1, GPRC:$rs1, GPRC:$rs2),
|
|
(C_SUB GPRC:$rs1, GPRC:$rs2)>;
|
|
def : CompressPat<(XOR GPRC:$rs1, GPRC:$rs1, GPRC:$rs2),
|
|
(C_XOR GPRC:$rs1, GPRC:$rs2)>;
|
|
def : CompressPat<(XOR GPRC:$rs1, GPRC:$rs2, GPRC:$rs1),
|
|
(C_XOR GPRC:$rs1, GPRC:$rs2)>;
|
|
def : CompressPat<(OR GPRC:$rs1, GPRC:$rs1, GPRC:$rs2),
|
|
(C_OR GPRC:$rs1, GPRC:$rs2)>;
|
|
def : CompressPat<(OR GPRC:$rs1, GPRC:$rs2, GPRC:$rs1),
|
|
(C_OR GPRC:$rs1, GPRC:$rs2)>;
|
|
def : CompressPat<(AND GPRC:$rs1, GPRC:$rs1, GPRC:$rs2),
|
|
(C_AND GPRC:$rs1, GPRC:$rs2)>;
|
|
def : CompressPat<(AND GPRC:$rs1, GPRC:$rs2, GPRC:$rs1),
|
|
(C_AND GPRC:$rs1, GPRC:$rs2)>;
|
|
} // Predicates = [HasStdExtC]
|
|
|
|
let Predicates = [HasStdExtC, IsRV64] in {
|
|
def : CompressPat<(SUBW GPRC:$rs1, GPRC:$rs1, GPRC:$rs2),
|
|
(C_SUBW GPRC:$rs1, GPRC:$rs2)>;
|
|
def : CompressPat<(ADDW GPRC:$rs1, GPRC:$rs1, GPRC:$rs2),
|
|
(C_ADDW GPRC:$rs1, GPRC:$rs2)>;
|
|
def : CompressPat<(ADDW GPRC:$rs1, GPRC:$rs2, GPRC:$rs1),
|
|
(C_ADDW GPRC:$rs1, GPRC:$rs2)>;
|
|
} // Predicates = [HasStdExtC, IsRV64]
|
|
|
|
let Predicates = [HasStdExtC] in {
|
|
def : CompressPat<(JAL X0, simm12_lsb0:$offset),
|
|
(C_J simm12_lsb0:$offset)>;
|
|
def : CompressPat<(BEQ GPRC:$rs1, X0, simm9_lsb0:$imm),
|
|
(C_BEQZ GPRC:$rs1, simm9_lsb0:$imm)>;
|
|
def : CompressPat<(BNE GPRC:$rs1, X0, simm9_lsb0:$imm),
|
|
(C_BNEZ GPRC:$rs1, simm9_lsb0:$imm)>;
|
|
} // Predicates = [HasStdExtC]
|
|
|
|
// Quadrant 2
|
|
let Predicates = [HasStdExtC] in {
|
|
def : CompressPat<(SLLI GPRNoX0:$rs1, GPRNoX0:$rs1, uimmlog2xlennonzero:$imm),
|
|
(C_SLLI GPRNoX0:$rs1, uimmlog2xlennonzero:$imm)>;
|
|
} // Predicates = [HasStdExtC]
|
|
|
|
let Predicates = [HasStdExtC, HasStdExtD] in {
|
|
def : CompressPat<(FLD FPR64:$rd, SP:$rs1, uimm9_lsb000:$imm),
|
|
(C_FLDSP FPR64:$rd, SP:$rs1, uimm9_lsb000:$imm)>;
|
|
} // Predicates = [HasStdExtC, HasStdExtD]
|
|
|
|
let Predicates = [HasStdExtC] in {
|
|
def : CompressPat<(LW GPRNoX0:$rd, SP:$rs1, uimm8_lsb00:$imm),
|
|
(C_LWSP GPRNoX0:$rd, SP:$rs1, uimm8_lsb00:$imm)>;
|
|
} // Predicates = [HasStdExtC]
|
|
|
|
let Predicates = [HasStdExtC, HasStdExtF, IsRV32] in {
|
|
def : CompressPat<(FLW FPR32:$rd, SP:$rs1, uimm8_lsb00:$imm),
|
|
(C_FLWSP FPR32:$rd, SP:$rs1, uimm8_lsb00:$imm)>;
|
|
} // Predicates = [HasStdExtC, HasStdExtF, IsRV32]
|
|
|
|
let Predicates = [HasStdExtC, IsRV64] in {
|
|
def : CompressPat<(LD GPRNoX0:$rd, SP:$rs1, uimm9_lsb000:$imm),
|
|
(C_LDSP GPRNoX0:$rd, SP:$rs1, uimm9_lsb000:$imm)>;
|
|
} // Predicates = [HasStdExtC, IsRV64]
|
|
|
|
let Predicates = [HasStdExtC] in {
|
|
def : CompressPat<(JALR X0, GPRNoX0:$rs1, 0),
|
|
(C_JR GPRNoX0:$rs1)>;
|
|
def : CompressPat<(ADD GPRNoX0:$rs1, X0, GPRNoX0:$rs2),
|
|
(C_MV GPRNoX0:$rs1, GPRNoX0:$rs2)>;
|
|
def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs2, X0),
|
|
(C_MV GPRNoX0:$rs1, GPRNoX0:$rs2)>;
|
|
def : CompressPat<(ADDI GPRNoX0:$rs1, GPRNoX0:$rs2, 0),
|
|
(C_MV GPRNoX0:$rs1, GPRNoX0:$rs2)>;
|
|
def : CompressPat<(EBREAK), (C_EBREAK)>;
|
|
def : CompressPat<(JALR X1, GPRNoX0:$rs1, 0),
|
|
(C_JALR GPRNoX0:$rs1)>;
|
|
def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs1, GPRNoX0:$rs2),
|
|
(C_ADD GPRNoX0:$rs1, GPRNoX0:$rs2)>;
|
|
def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs2, GPRNoX0:$rs1),
|
|
(C_ADD GPRNoX0:$rs1, GPRNoX0:$rs2)>;
|
|
} // Predicates = [HasStdExtC]
|
|
|
|
let Predicates = [HasStdExtC, HasStdExtD] in {
|
|
def : CompressPat<(FSD FPR64:$rs2, SP:$rs1, uimm9_lsb000:$imm),
|
|
(C_FSDSP FPR64:$rs2, SP:$rs1, uimm9_lsb000:$imm)>;
|
|
} // Predicates = [HasStdExtC, HasStdExtD]
|
|
|
|
let Predicates = [HasStdExtC] in {
|
|
def : CompressPat<(SW GPR:$rs2, SP:$rs1, uimm8_lsb00:$imm),
|
|
(C_SWSP GPR:$rs2, SP:$rs1, uimm8_lsb00:$imm)>;
|
|
} // Predicates = [HasStdExtC]
|
|
|
|
let Predicates = [HasStdExtC, HasStdExtF, IsRV32] in {
|
|
def : CompressPat<(FSW FPR32:$rs2, SP:$rs1, uimm8_lsb00:$imm),
|
|
(C_FSWSP FPR32:$rs2, SP:$rs1, uimm8_lsb00:$imm)>;
|
|
} // Predicates = [HasStdExtC, HasStdExtF, IsRV32]
|
|
|
|
let Predicates = [HasStdExtC, IsRV64] in {
|
|
def : CompressPat<(SD GPR:$rs2, SP:$rs1, uimm9_lsb000:$imm),
|
|
(C_SDSP GPR:$rs2, SP:$rs1, uimm9_lsb000:$imm)>;
|
|
} // Predicates = [HasStdExtC, IsRV64]
|