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e37295579e
Software pipelining is an optimization for improving ILP by overlapping loop iterations. Swing Modulo Scheduling (SMS) is an implementation of software pipelining that attempts to reduce register pressure and generate efficient pipelines with a low compile-time cost. This implementaion of SMS is a target-independent back-end pass. When enabled, the pass should run just prior to the register allocation pass, while the machine IR is in SSA form. If the pass is successful, then the original loop is replaced by the optimized loop. The optimized loop contains one or more prolog blocks, the pipelined kernel, and one or more epilog blocks. This pass is enabled for Hexagon only. To enable for other targets, a couple of target specific hooks must be implemented, and the pass needs to be called from the target's TargetMachine implementation. Differential Review: http://reviews.llvm.org/D16829 llvm-svn: 277169
76 lines
3.0 KiB
LLVM
76 lines
3.0 KiB
LLVM
; RUN: llc -march=hexagon -mcpu=hexagonv60 -enable-bsb-sched=0 -enable-pipeliner < %s | FileCheck %s
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; RUN: llc -march=hexagon -mcpu=hexagonv5 -enable-pipeliner < %s | FileCheck %s
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; From coremark. Test that we pipeline the matrix multiplication bitextract
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; function. The pipelined code should have two packets.
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; CHECK: loop0(.LBB0_[[LOOP:.]],
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; CHECK: .LBB0_[[LOOP]]:
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; CHECK: = extractu([[REG2:(r[0-9]+)]],
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; CHECK: = extractu([[REG2]],
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; CHECK: [[REG0:(r[0-9]+)]] = memh
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; CHECK: [[REG1:(r[0-9]+)]] = memh
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; CHECK: += mpyi
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; CHECK: [[REG2]] = mpyi([[REG0]], [[REG1]])
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; CHECK: endloop0
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%union_h2_sem_t = type { i32 }
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@sem_i = common global [0 x %union_h2_sem_t] zeroinitializer, align 4
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define void @matrix_mul_matrix_bitextract(i32 %N, i32* %C, i16* %A, i16* %B) {
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entry:
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%cmp53 = icmp eq i32 %N, 0
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br i1 %cmp53, label %for_end27, label %for_body3_lr_ph_us
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for_body3_lr_ph_us:
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%i_054_us = phi i32 [ %inc26_us, %for_cond1_for_inc25_crit_edge_us ], [ 0, %entry ]
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%0 = mul i32 %i_054_us, %N
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%arrayidx9_us_us_gep = getelementptr i16, i16* %A, i32 %0
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br label %for_body3_us_us
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for_cond1_for_inc25_crit_edge_us:
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%inc26_us = add i32 %i_054_us, 1
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%exitcond89 = icmp eq i32 %inc26_us, %N
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br i1 %exitcond89, label %for_end27, label %for_body3_lr_ph_us
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for_body3_us_us:
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%j_052_us_us = phi i32 [ %inc23_us_us, %for_cond4_for_inc22_crit_edge_us_us ], [ 0, %for_body3_lr_ph_us ]
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%add_us_us = add i32 %j_052_us_us, %0
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%arrayidx_us_us = getelementptr inbounds i32, i32* %C, i32 %add_us_us
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store i32 0, i32* %arrayidx_us_us, align 4
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br label %for_body6_us_us
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for_cond4_for_inc22_crit_edge_us_us:
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store i32 %add21_us_us, i32* %arrayidx_us_us, align 4
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%inc23_us_us = add i32 %j_052_us_us, 1
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%exitcond88 = icmp eq i32 %inc23_us_us, %N
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br i1 %exitcond88, label %for_cond1_for_inc25_crit_edge_us, label %for_body3_us_us
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for_body6_us_us:
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%1 = phi i32 [ 0, %for_body3_us_us ], [ %add21_us_us, %for_body6_us_us ]
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%arrayidx9_us_us_phi = phi i16* [ %arrayidx9_us_us_gep, %for_body3_us_us ], [ %arrayidx9_us_us_inc, %for_body6_us_us ]
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%k_050_us_us = phi i32 [ 0, %for_body3_us_us ], [ %inc_us_us, %for_body6_us_us ]
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%2 = load i16, i16* %arrayidx9_us_us_phi, align 2
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%conv_us_us = sext i16 %2 to i32
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%mul10_us_us = mul i32 %k_050_us_us, %N
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%add11_us_us = add i32 %mul10_us_us, %j_052_us_us
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%arrayidx12_us_us = getelementptr inbounds i16, i16* %B, i32 %add11_us_us
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%3 = load i16, i16* %arrayidx12_us_us, align 2
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%conv13_us_us = sext i16 %3 to i32
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%mul14_us_us = mul nsw i32 %conv13_us_us, %conv_us_us
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%shr47_us_us = lshr i32 %mul14_us_us, 2
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%and_us_us = and i32 %shr47_us_us, 15
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%shr1548_us_us = lshr i32 %mul14_us_us, 5
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%and16_us_us = and i32 %shr1548_us_us, 127
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%mul17_us_us = mul i32 %and_us_us, %and16_us_us
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%add21_us_us = add i32 %mul17_us_us, %1
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%inc_us_us = add i32 %k_050_us_us, 1
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%exitcond87 = icmp eq i32 %inc_us_us, %N
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%arrayidx9_us_us_inc = getelementptr i16, i16* %arrayidx9_us_us_phi, i32 1
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br i1 %exitcond87, label %for_cond4_for_inc22_crit_edge_us_us, label %for_body6_us_us
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for_end27:
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ret void
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}
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