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121 lines
3.3 KiB
LLVM
121 lines
3.3 KiB
LLVM
; RUN: llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s
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; arm64 has a separate copy: aarch64-large-frame.ll (codegen was too different).
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declare void @use_addr(i8*)
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@addr = global i8* null
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define void @test_bigframe() {
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; CHECK-LABEL: test_bigframe:
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; CHECK: .cfi_startproc
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%var1 = alloca i8, i32 20000000
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%var2 = alloca i8, i32 16
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%var3 = alloca i8, i32 20000000
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; CHECK: sub sp, sp, #496
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; CHECK: .cfi_def_cfa sp, 496
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; CHECK: str x30, [sp, #488]
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; Total adjust is 39999536
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; CHECK: movz [[SUBCONST:x[0-9]+]], #22576
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; CHECK: movk [[SUBCONST]], #610, lsl #16
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; CHECK: sub sp, sp, [[SUBCONST]]
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; CHECK: .cfi_def_cfa sp, 40000032
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; CHECK: .cfi_offset x30, -8
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; Total offset is 20000024
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; CHECK: movz [[VAR1OFFSET:x[0-9]+]], #11544
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; CHECK: movk [[VAR1OFFSET]], #305, lsl #16
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; CHECK: add {{x[0-9]+}}, sp, [[VAR1OFFSET]]
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store volatile i8* %var1, i8** @addr
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%var1plus2 = getelementptr i8* %var1, i32 2
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store volatile i8* %var1plus2, i8** @addr
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; CHECK: movz [[VAR2OFFSET:x[0-9]+]], #11528
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; CHECK: movk [[VAR2OFFSET]], #305, lsl #16
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; CHECK: add {{x[0-9]+}}, sp, [[VAR2OFFSET]]
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store volatile i8* %var2, i8** @addr
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%var2plus2 = getelementptr i8* %var2, i32 2
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store volatile i8* %var2plus2, i8** @addr
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store volatile i8* %var3, i8** @addr
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%var3plus2 = getelementptr i8* %var3, i32 2
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store volatile i8* %var3plus2, i8** @addr
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; CHECK: movz [[ADDCONST:x[0-9]+]], #22576
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; CHECK: movk [[ADDCONST]], #610, lsl #16
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; CHECK: add sp, sp, [[ADDCONST]]
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; CHECK: .cfi_endproc
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ret void
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}
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define void @test_mediumframe() {
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; CHECK-LABEL: test_mediumframe:
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%var1 = alloca i8, i32 1000000
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%var2 = alloca i8, i32 16
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%var3 = alloca i8, i32 1000000
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; CHECK: sub sp, sp, #496
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; CHECK: str x30, [sp, #488]
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; CHECK: sub sp, sp, #688
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; CHECK-NEXT: sub sp, sp, #488, lsl #12
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store volatile i8* %var1, i8** @addr
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; CHECK: add [[VAR1ADDR:x[0-9]+]], sp, #600
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; CHECK: add [[VAR1ADDR]], [[VAR1ADDR]], #244, lsl #12
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%var1plus2 = getelementptr i8* %var1, i32 2
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store volatile i8* %var1plus2, i8** @addr
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; CHECK: add [[VAR1PLUS2:x[0-9]+]], {{x[0-9]+}}, #2
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store volatile i8* %var2, i8** @addr
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; CHECK: add [[VAR2ADDR:x[0-9]+]], sp, #584
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; CHECK: add [[VAR2ADDR]], [[VAR2ADDR]], #244, lsl #12
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%var2plus2 = getelementptr i8* %var2, i32 2
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store volatile i8* %var2plus2, i8** @addr
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; CHECK: add [[VAR2PLUS2:x[0-9]+]], {{x[0-9]+}}, #2
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store volatile i8* %var3, i8** @addr
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%var3plus2 = getelementptr i8* %var3, i32 2
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store volatile i8* %var3plus2, i8** @addr
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; CHECK: add sp, sp, #688
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; CHECK: add sp, sp, #488, lsl #12
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; CHECK: ldr x30, [sp, #488]
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; CHECK: add sp, sp, #496
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ret void
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}
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@bigspace = global [8 x i64] zeroinitializer
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; If temporary registers are allocated for adjustment, they should *not* clobber
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; argument registers.
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define void @test_tempallocation([8 x i64] %val) nounwind {
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; CHECK-LABEL: test_tempallocation:
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%var = alloca i8, i32 1000000
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; CHECK: sub sp, sp,
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; Make sure the prologue is reasonably efficient
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; CHECK-NEXT: stp x29, x30, [sp,
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; CHECK-NEXT: stp x25, x26, [sp,
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; CHECK-NEXT: stp x23, x24, [sp,
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; CHECK-NEXT: stp x21, x22, [sp,
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; CHECK-NEXT: stp x19, x20, [sp,
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; Make sure we don't trash an argument register
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; CHECK-NOT: movz {{x[0-7],}}
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; CHECK: sub sp, sp,
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; CHECK-NOT: movz {{x[0-7],}}
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; CHECK: bl use_addr
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call void @use_addr(i8* %var)
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store [8 x i64] %val, [8 x i64]* @bigspace
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ret void
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; CHECK: ret
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}
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