Alex Bradbury deac507c70 [RISCV] Accept fmv.s.x and fmv.x.s as mnemonic aliases for fmv.w.x and fmv.x.w ... These instructions were renamed in version 2.2 of the user-level ISA spec, but the old name should also be accepted by standard tools. llvm-svn: 335154		2018-06-20 18:42:25 +00:00
..
AsmParser	[RISCV] AsmParser support for the li pseudo instruction	2018-06-07 15:35:47 +00:00
Disassembler	Rename DEBUG macro to LLVM_DEBUG.	2018-05-14 12:53:11 +00:00
InstPrinter
MCTargetDesc	Fix compilation of WebAssembly and RISCV after r334078	2018-06-06 10:57:50 +00:00
TargetInfo
CMakeLists.txt
LLVMBuild.txt
RISCV.h
RISCV.td	[RISCV] Define FeatureRelax and shouldForceRelocation for RISCV linker relaxation	2018-05-15 01:28:50 +00:00
RISCVAsmPrinter.cpp
RISCVCallingConv.td
RISCVFrameLowering.cpp
RISCVFrameLowering.h
RISCVInstrFormats.td	[RISCV] AsmParser support for the li pseudo instruction	2018-06-07 15:35:47 +00:00
RISCVInstrFormatsC.td
RISCVInstrInfo.cpp	[RISCV] Lower the tail pseudoinstruction	2018-05-23 22:44:08 +00:00
RISCVInstrInfo.h
RISCVInstrInfo.td	[RISCV] Add InstAlias definitions for sgt and sgtu	2018-06-20 12:54:02 +00:00
RISCVInstrInfoA.td	[RISCV] Add codegen support for atomic load/stores with RV32A	2018-06-13 12:04:51 +00:00
RISCVInstrInfoC.td
RISCVInstrInfoD.td	[RISCV] Add InstAlias definitions for fgt.{s|d}, fge.{s|d}	2018-06-20 14:03:02 +00:00
RISCVInstrInfoF.td	[RISCV] Accept fmv.s.x and fmv.x.s as mnemonic aliases for fmv.w.x and fmv.x.w	2018-06-20 18:42:25 +00:00
RISCVInstrInfoM.td
RISCVISelDAGToDAG.cpp	[RISCV] Add peepholes for Global Address lowering patterns	2018-05-29 19:34:54 +00:00
RISCVISelLowering.cpp	[RISCV] Add codegen support for atomic load/stores with RV32A	2018-06-13 12:04:51 +00:00
RISCVISelLowering.h	[RISCV] Add codegen support for atomic load/stores with RV32A	2018-06-13 12:04:51 +00:00
RISCVMachineFunctionInfo.h
RISCVMCInstLower.cpp
RISCVRegisterInfo.cpp	[RISCV] Set isReMaterializable on ADDI and LUI instructions	2018-05-17 15:51:37 +00:00
RISCVRegisterInfo.h	[RISCV] Set isReMaterializable on ADDI and LUI instructions	2018-05-17 15:51:37 +00:00
RISCVRegisterInfo.td	[RISCV] Lower the tail pseudoinstruction	2018-05-23 22:44:08 +00:00
RISCVSubtarget.cpp
RISCVSubtarget.h	[RISCV] Define FeatureRelax and shouldForceRelocation for RISCV linker relaxation	2018-05-15 01:28:50 +00:00
RISCVTargetMachine.cpp	[RISCV] Codegen support for atomic operations on RV32I	2018-06-13 11:58:46 +00:00
RISCVTargetMachine.h
RISCVTargetObjectFile.cpp
RISCVTargetObjectFile.h